公开(公告)号：US20190155608A1

公开(公告)日：2019-05-23

申请号：US16193935

申请日：2018-11-16

Applicant: QUALCOMM Incorporated

Inventor： Arthur PERAIS ,  Michael Scott MCILVAINE ,  Rami Mohammad A. AL SHEIKH ,  Robert Douglas CLANCY ,  Luke YEN ,  Rodney Wayne SMITH

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

Abstract: Aspects of the present disclosure include a method, a device, and a computer-readable medium for restarting an instruction pipeline of a processor that includes a decoupled fetcher. A method comprises detecting, in a processor, a re-fetch event, wherein the processor includes an instruction unit (IU) configured to fetch instructions from a decoupled fetcher (DCF), and simultaneously flushing the IU and the DCF in response to detecting of the re-fetch event.

公开(公告)号：US20180074568A1

公开(公告)日：2018-03-15

申请号：US15814361

申请日：2017-11-15

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Anil KRISHNA ,  Raguram DAMODARAN ,  Jeffrey Todd BRIDGES ,  Ryan WELLS ,  Norman GARGASH ,  Rodney Wayne SMITH

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

公开(公告)号：US20170060593A1

公开(公告)日：2017-03-02

申请号：US14843921

申请日：2015-09-02

Applicant: QUALCOMM Incorporated

Inventor： Anil KRISHNA ,  Rodney Wayne SMITH ,  Sandeep Suresh NAVADA ,  Shivam PRIYADARSHI ,  Niket Kumar CHOUDHARY ,  Raguram DAMODARAN

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30105 ,  G06F9/30138 ,  G06F9/384 ,  G06F9/3867

Abstract: Systems and methods relate to a hierarchical register file system including a level 1 physical register file (L1 PRF) and a backing physical register file (PRF). A subset of productions of instructions executed in an instruction pipeline of a processor which have a high likelihood of use for one or more future instructions are identified. The subset of productions are stored in the L1 PRF, while all productions are stored in the backing PRF.

Abstract translation: 系统和方法涉及包括1级物理寄存器文件（L1 PRF）和后置物理寄存器文件（PRF）的分级寄存器文件系统。 识别在处理器的指令流水线中执行的指令的生成的子集，其具有用于一个或多个未来指令的高似然性。 生产的子集存储在L1 PRF中，而所有生产都存储在后备PRF中。

公开(公告)号：US20190332385A1

公开(公告)日：2019-10-31

申请号：US15963126

申请日：2018-04-26

Applicant: QUALCOMM Incorporated

Inventor： Rodney Wayne SMITH ,  Raghavan MADHAVAN ,  Luke YEN ,  Shivam PRIYADARSHI ,  Yusuf Cagatay TEKMEN

IPC: G06F9/38

Abstract: In certain aspects of the disclosure, an apparatus comprises a first scheduling pool associated with a first minimum scheduling latency and a second scheduling pool associated with a second minimum scheduling latency, the second minimum scheduling latency greater than the first minimum scheduling latency. A common instruction picker is coupled to both the first scheduling pool and the second scheduling pool. The common instruction picker may be configured to select a first instruction from the first scheduling pool and a second instruction from the second scheduling pool, and then choose either the first instruction or second instruction for dispatch according to a picking policy.

公开(公告)号：US20170090508A1

公开(公告)日：2017-03-30

申请号：US14865092

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Anil KRISHNA ,  Raguram DAMODARAN ,  Jeffrey Todd BRIDGES ,  Thomas Philip SPEIER ,  Rodney Wayne SMITH ,  Keith Alan BOWMAN ,  David Joseph Winston HANSQUINE

IPC: G06F1/08 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3861 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/60 ,  Y02D10/126 ,  Y02D10/152

Abstract: The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a last level cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and provided that the total number of processor cycles since the last level cache miss does not exceed some specified number.

公开(公告)号：US20150268959A1

公开(公告)日：2015-09-24

申请号：US14221430

申请日：2014-03-21

Applicant: QUALCOMM Incorporated

Inventor： Anil KRISHNA ,  Weidan WU ,  Sandeep Suresh NAVADA ,  Niket Kumar CHOUDHARY ,  Rodney Wayne SMITH

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30098 ,  G06F9/3832 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3861

Abstract: Identifying two instructions without intervening potential pipeline flushers that write to the same architected destination register in order to free the physical register corresponding to the older of the two instructions.

Abstract translation: 识别两个指令，而不会插入写入同一架构目标寄存器的潜在管道冲洗器，以便释放与两个指令中较旧的对应的物理寄存器。

公开(公告)号：US20170255569A1

公开(公告)日：2017-09-07

申请号：US15057121

申请日：2016-03-01

Applicant: QUALCOMM Incorporated

Inventor： Thomas Andrew SARTORIUS ,  James Norris DIEFFENDERFER ,  Michael William MORROW ,  Jeffrey Todd BRIDGES ,  Michael Scott MCILVAINE ,  Rodney Wayne SMITH ,  Kenneth Alan DOCKSER ,  Thomas Philip SPEIER

IPC: G06F12/12 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/123 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/126 ,  G06F2212/604 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/684

Abstract: Systems and methods for managing access to a cache relate to determining one or more execute permissions associated with a write-address of a write-request to the cache. The cache may be a unified cache for storing data as well as instructions. If there is a write-miss in the cache for the write-request, a cache controller may determine whether to implement a write-allocate policy or a write-no-allocate policy for servicing the write-miss, based on the one or more execute permissions. The one or more execute permissions can relate to a privilege level associated with the write-address. Execute permissions of a producing agent which generated the write-request and an execute permission of a consuming agent which can execute from the write-address may be based on the privilege levels of the producing agent and the consuming agent, respectively.

公开(公告)号：US20170046160A1

公开(公告)日：2017-02-16

申请号：US15086055

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Kiran Ravi SETH ,  Rodney Wayne SMITH ,  Yusuf Cagatay TEKMEN ,  Raghaven MADHAVAN

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30098

Abstract: Systems and methods of handling a register file include, in a first instruction set architecture (ISA) mode assigning a first subset of tracking resources to logical registers of a first logical register subset for tracking mappings to full granularity and first lower granularity physical registers of a first physical register subset, and assigning a second subset of tracking resources to logical registers of a second logical register subset for tracking mappings to second lower granularity physical registers of the first physical register subset. The second subset of tracking resources are configured for tracking at least the logical registers of the second logical register subset mappings to physical registers of a second physical register subset in a second ISA mode, wherein the second physical register subset is available to the second ISA mode but not the first ISA mode.

Abstract translation: 处理寄存器文件的系统和方法包括在第一指令集架构（ISA）模式中，将跟踪资源的第一子集分配给第一逻辑寄存器子集的逻辑寄存器，以将跟踪映射到全粒度，以及第一下级粒度物理寄存器 第一物理寄存器子集，以及将跟踪资源的第二子集分配给第二逻辑寄存器子集的逻辑寄存器，用于跟踪与第一物理寄存器子集的第二较低粒度物理寄存器的映射。 跟踪资源的第二子集被配置用于在第二ISA模式中至少跟踪第二逻辑寄存器子集映射到第二物理寄存器子集的物理寄存器的逻辑寄存器，其中第二物理寄存器子集可用于第二ISA模式 但不是第一个ISA模式。

公开(公告)号：US20200004550A1

公开(公告)日：2020-01-02

申请号：US16024725

申请日：2018-06-29

Applicant: QUALCOMM Incorporated

Inventor： Harsh THAKKER ,  Thomas Philip SPEIER ,  Rodney Wayne SMITH ,  Kevin JAGET ,  James Norris DIEFFENDERFER ,  Michael MORROW ,  Pritha GHOSHAL ,  Yusuf Cagatay TEKMEN ,  Brian STEMPEL ,  Sang Hoon LEE ,  Manish GARG

IPC: G06F9/38 ,  G06F9/30

Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

公开(公告)号：US20170046164A1

公开(公告)日：2017-02-16

申请号：US14865150

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Raghavan MADHAVAN ,  Kiran RAVI SETH ,  Yusuf Cagatay TEKMEN ,  Rodney Wayne SMITH

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3838 ,  G06F9/3842

Abstract: A load instruction, for loading a register among a set of registers, is scheduled. Associated with scheduling the load instruction, a register dependency vector, corresponding to the register, is set to a state identifying the load instruction. A consumer instruction is scheduled, having a set of operand register and a target register, the register being in the set of operand registers. A target register dependency vector, corresponding to the target register is set in the memory. Based at least in part on the register being in the set of operand registers, a value of the target register dependency vector identifies the load instruction. Optionally, upon receiving a cache miss notice associated with the load instruction, the target register dependency vector is retrieved.

Abstract translation: 调度用于在一组寄存器中加载寄存器的加载指令。 与调度加载指令相关联，将与寄存器对应的寄存器依赖向量设置为标识加载指令的状态。 消费者指令被调度，具有一组操作数寄存器和目标寄存器，寄存器位于操作数寄存器组中。 在存储器中设置与目标寄存器对应的目标寄存器依赖向量。 至少部分地基于在操作数寄存器组中的寄存器，目标寄存器依赖性向量的值标识加载指令。 可选地，在接收到与加载指令相关联的高速缓存未命中通知时，检索目标寄存器相关性向量。