公开(公告)号：US12284715B2

公开(公告)日：2025-04-22

申请号：US17928200

申请日：2020-07-28

Applicant: QUALCOMM Incorporated

Inventor： Nan Zhang ,  Yongjun Xu ,  Long Han

IPC: H04W76/28 ,  H04W72/12 ,  H04W72/50

Abstract: Aspects of the present disclosure include methods, apparatuses, and computer readable media for determining a connected mode discontinuous reception (C-DRX) short cycle value, transmitting a C-DRX short cycle request to a base station, the C-DRX short cycle request including the C-DRX short cycle value, receiving a first confirmation indicating the base station accepting the C-DRX short cycle value associated with the C-DRX short cycle request, determining an averaging window value based on the C-DRX short cycle value, transmitting an averaging window request to the base station, the averaging window request including the averaging window value, receiving a second confirmation indicating the base station accepting the averaging window value associated with the averaging window request, and communicating with the base station based on the C-DRX short cycle value and the averaging window value.

公开(公告)号：US12170071B2

公开(公告)日：2024-12-17

申请号：US18424699

申请日：2024-01-26

Applicant: QUALCOMM Incorporated

Inventor： Nan Zhang ,  Long Han ,  Yongjun Xu

IPC: G09G3/36 ,  G09G5/00 ,  G09G5/18

Abstract: Methods and apparatuses are provided for alignment of hardware and software Vsync signals through filtering out delayed timestamp signals in a hardware timestamp signal used to generate the software Vsync. The alignment may occur when a display client is operating in a video mode but not a command mode. A compositor or processing unit may receive a hardware Vsync signal from a display using a video mode, generate a hardware timestamp signal based on the hardware Vsync signal, determine a delay for a pulse in the hardware timestamp signal based on a delay for a set of previous frames, determine whether the delay for the pulse is over a threshold, and control rendering and transmission of a frame to the display based on the delay for the pulse being over the threshold. Thus, accurate Vsync signal synchronization may occur.

公开(公告)号：US12249017B2

公开(公告)日：2025-03-11

申请号：US17794876

申请日：2020-02-21

Applicant: QUALCOMM Incorporated

Inventor： Yongjun Xu ,  Nan Zhang ,  Wenkai Yao ,  Long Han

IPC: G06T15/00 ,  G06F1/12 ,  G06T1/20

Abstract: Devices and methods for reducing a DPU transfer time to compensate for a delayed GPU render time. After completion of rendering a second frame that follows a first frame, a frame processor determines whether the first frame is currently transferring to a display panel or has already been transferred to the display panel. At least one clock is used with a first set of clock speeds when the first frame is determined to be currently transferring and used with a second set of clock speeds when the first frame is determined to have already been transferred, the second set of clock speeds being faster than the first set of clock speeds. After completion of the transfer of the first frame, the second frame is transferred based on the set of clock speeds.

公开(公告)号：US11935502B2

公开(公告)日：2024-03-19

申请号：US17758286

申请日：2020-12-30

Applicant: QUALCOMM Incorporated

Inventor： Nan Zhang ,  Long Han ,  Yongjun Xu

IPC: G09G3/36 ,  G09G5/00 ,  G09G5/18

CPC classification number: G09G5/005 ,  G09G5/18

Abstract: Aspects of the present disclosure can receive a hardware Vsync signal from a display, generate a hardware timestamp signal based on the hardware Vsync signal, determine an error for a pulse in the hardware timestamp signal, determine whether the error for the pulse is over a threshold, synchronize a software Vsync signal based on the hardware timestamp signal, wherein the pulse of the hardware timestamp signal is ignored in synchronization based on whether the error is above the threshold, and control rendering and transmission of a frame to the display based on the synchronized software Vsync signal.