公开(公告)号：US20180337660A1

公开(公告)日：2018-11-22

申请号：US15673261

申请日：2017-08-09

Applicant: QUALCOMM Incorporated

Inventor： Makar SNAI

IPC: H03H11/44 ,  H04B1/04 ,  H03H7/09 ,  H03H11/04 ,  H03H11/34 ,  H03H11/52 ,  H03H7/38

Abstract: An impedance converter circuit achieves negative capacitance and/or negative inductance for radio frequency (RF) front end impedance matching for low noise amplifier (LNA) designs. The impedance converter circuit includes a first transistor coupled to a first RF input at a source of the first transistor. The impedance converter circuit also includes a second transistor coupled to a second RF input at a source of the second transistor. The second transistor is cross-coupled to the first transistor to form a cross-coupled pair of transistors. The cross-coupled pair of transistors is configured to generate a negative capacitance or a negative inductance based on a load impedance coupled to a drain of the first transistor and a drain of the second transistor.

公开(公告)号：US20220131505A1

公开(公告)日：2022-04-28

申请号：US17081873

申请日：2020-10-27

Applicant: QUALCOMM Incorporated

Inventor： Makar SNAI ,  Manohar SEETHARAM

IPC: H03F1/26 ,  H03F1/22

Abstract: An active feedback low-noise amplifier includes a feedback transistor whose source couples through a feedback path to an input signal node. A bias transistor biases the source of the feedback transistor with a bias current responsive to an input signal carried on the input signal node.

公开(公告)号：US20200036345A1

公开(公告)日：2020-01-30

申请号：US16519877

申请日：2019-07-23

Applicant: QUALCOMM Incorporated

Inventor： Makar SNAI ,  Manohar SEETHARAM ,  Ehab ABDEL GHANY ,  Vinod PANIKKATH

IPC: H03F1/26 ,  H04B1/16 ,  H03F3/193

Abstract: Certain aspects of the present disclosure are directed to a circuit for signal processing. The circuit generally includes a first transformer having a first inductive element magnetically coupled with a second inductive element, and a second transformer having a third inductive element magnetically coupled with a fourth inductive element, wherein the first inductive element is coupled in series with the third inductive element. In certain aspects, the circuit also includes a first switch coupled in parallel with the third inductive element, a capacitive element coupled in parallel with the fourth inductive element, wherein a notch is formed at least by the capacitive element and the fourth inductive element, the notch circuit coupled in series with the second inductive element, and a second switch coupled in parallel with the fourth inductive element.