公开(公告)号：US20190043817A1

公开(公告)日：2019-02-07

申请号：US16132315

申请日：2018-09-14

Applicant: QUALCOMM Incorporated

Inventor： Manoj KADADE ,  Haiyong XU ,  Ruey Kae ZANG ,  Yue LI ,  Xiaonan ZHANG ,  Christine HAU-RIEGE

IPC: H01L23/00

Abstract: The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising a WLP contact and a component within the WLP layer associated with a component depth. A conductive pillar is disposed on the WLP contact and comprises an opposite surface that forms an array pad. The package further comprises a mold over the WLP layer and at least partially surrounding the conductive pillar, wherein the mold compound and the array pad form a substantially planar land grid array (LGA) contact surface that is configured to couple the package to a land grid array. The LGA contact surface has a height that is equal to a selected LGA component height, and the selected LGA component height is equal to a difference between a keepout distance associated with a characteristic of the component within the WLP layer and the component depth.