公开(公告)号：US20250096207A1

公开(公告)日：2025-03-20

申请号：US18470344

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Yue LI ,  Durodami LISK ,  Ryan LANE ,  Darko POPOVIC

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: A package comprising a first metallization portion; a first integrated device coupled to the first metallization portion; a bridge coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion; a second metallization portion coupled to the bridge and the encapsulation layer, such that the first integrated device, the bridge and the encapsulation layer are located between the first metallization portion and the second metallization portion, and a second integrated device coupled to the second metallization portion, wherein the second integrated device and the bridge at least partially vertically overlap.

公开(公告)号：US20210375742A1

公开(公告)日：2021-12-02

申请号：US16888516

申请日：2020-05-29

Applicant: QUALCOMM Incorporated

Inventor： Yue LI ,  Li-Sheng WENG ,  Yangyang SUN

IPC: H01L23/50 ,  H01L23/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a die, having a pad layer structure on back-end-of-line layers on a substrate. The die also includes a metallization routing layer on the pad layer structure, and a first under bump metallization layer on the metallization routing layer. The IC package also includes a patterned seed layer on a surface of the die to contact the first under bump metallization layer. The IC package further includes a first package bump on the first under bump metallization layer.

公开(公告)号：US20180053740A1

公开(公告)日：2018-02-22

申请号：US15243923

申请日：2016-08-22

Applicant: QUALCOMM Incorporated

Inventor： Manoj KAKADE ,  Haiyong XU ,  Ruey Kae ZANG ,  Yue LI ,  Xiaonan ZHANG ,  Christine HAU-RIEGE

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2924/07025 ,  H01L2924/1206 ,  H01L2924/15313 ,  H05K1/111 ,  H05K1/185 ,  H05K2201/09472

Abstract: The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising first and second WLP contacts and first and second conductive pillars disposed on the first and second WLP contacts. Each conductive pillar may comprise a surface opposite the WLP contact that forms an array pad. The array pads may have different sizes. The package may further comprise a mold over the WLP layer and at least partially surrounding the conductive pillars, wherein the mold compound and the first array pads form a substantially planar LGA contact surface that is configured to couple the package to a land grid array.

公开(公告)号：US20170373032A1

公开(公告)日：2017-12-28

申请号：US15192825

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Jihoon OH ,  Ruey Kae ZANG ,  Lizabeth Ann KESER ,  Reynante Tamunan ALVARADO ,  Haiyong XU ,  Yue LI ,  Steve BEZUK

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5227 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/96 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/06131 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/14131 ,  H01L2224/1416 ,  H01L2224/14177 ,  H01L2224/96 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/2064 ,  H01L2924/381 ,  H01L2224/03 ,  H01L2224/11

Abstract: Disclosed is a fan-out wafer level packaging (FOWLP) apparatus includes a semiconductor die having at least one input/output (I/O) connection, a first plurality of package balls having a first package ball layout, a first conductive layer forming a first redistribution layer (RDL) and configured to electrically couple to the first plurality of package balls, and a second conductive layer forming a second RDL and including at least one conductive pillar configured to electrically couple the at least one I/O connection of the semiconductor die to the first conductive layer, wherein the second conductive layer enables the semiconductor die to be electrically coupled to a second plurality of package balls having a second package ball layout without a change in position of the at least one I/O connection of the semiconductor die.

公开(公告)号：US20240038831A1

公开(公告)日：2024-02-01

申请号：US17878758

申请日：2022-08-01

Applicant: QUALCOMM Incorporated

Inventor： Ryan LANE ,  Charles David PAYNTER ,  Durodami LISK ,  Darko POPOVIC ,  Yue LI ,  Shree Krishna PANDEY

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L24/16

Abstract: A package comprising a substrate and an integrated device. The substrate includes a core layer comprising a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, where the second trench capacitor device comprises a second front side and a second back side.

公开(公告)号：US20210125951A1

公开(公告)日：2021-04-29

申请号：US16665883

申请日：2019-10-28

Applicant: QUALCOMM Incorporated

Inventor： Li-Sheng WENG ,  Yue LI ,  Yangyang SUN

IPC: H01L23/00

Abstract: An integrated device that includes a substrate, an interconnect portion and an interconnect structure. The interconnect portion is located over the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located over the interconnect portion. The interconnect structure includes an inner interconnect, a dielectric layer coupled to the inner interconnect, and an outer conductive layer coupled to the dielectric layer. The outer conductive layer is configured to operate as a shield for the inner interconnect.

公开(公告)号：US20200176417A1

公开(公告)日：2020-06-04

申请号：US16209723

申请日：2018-12-04

Applicant: QUALCOMM Incorporated

Inventor： Brigham NAVAJA ,  Yue LI ,  Kuiwon KANG ,  Soumyadipta BASU ,  Joan Rey Villarba BUOT

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/64 ,  H01L23/00 ,  H05K1/18

Abstract: The present disclosure generally relates to an integrated circuit having a stacked embedded passive substrate (EPS) structure formed therein. In particular, a substrate may have a cavity formed therein and the stacked EPS structure may include multiple passive components formed in the cavity to provide separate electrical paths for decoupling of the integrated circuit. Furthermore, the multiple passive components may each have two respective terminals such that the multiple passive components may support different voltage domains. Among other things, compared to conventional die-side and/or land-side passive components, the stacked EPS structure may advantageously reduce a z-axis height of the integrated circuit, reduce manufacturing costs, improve performance due to shorter electrical paths, and improve design routing through x-axis and y-axis space savings.

公开(公告)号：US20170005160A1

公开(公告)日：2017-01-05

申请号：US14973479

申请日：2015-12-17

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Yue LI ,  Ratibor RADOJCIC

IPC: H01L49/02 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/53228 ,  H01L28/75

Abstract: Copper (Cu) grain boundaries can move during a thermal cycle resulting in the Cu grain position being offset. Such Cu pumping can disturb the surface of a bottom metal, and can physically break a dielectric of a metal-insulator-metal (MIM) capacitor. By capping the bottom metal with an anchoring cap, Cu pumping is reduced or eliminated.

Abstract translation: 铜（Cu）晶界可以在热循环期间移动，导致Cu晶粒位置偏移。 这种Cu泵浦可能会干扰底部金属的表面，并且可以物理地破坏金属 - 绝缘体 - 金属（MIM）电容器的电介质。 通过用锚固帽盖住底部金属，减少或消除Cu泵送。

公开(公告)号：US20150364438A1

公开(公告)日：2015-12-17

申请号：US14303465

申请日：2014-06-12

Applicant: QUALCOMM Incorporated

Inventor： Haiyong XU ,  Manoj Ashok KAKADE ,  Hua GUAN ,  Yue LI ,  Xiaoming CHEN ,  Ruey Kae ZANG

IPC: H01L23/00 ,  B23K3/06

CPC classification number: H01L24/14 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/11 ,  H01L24/75 ,  H01L2224/1412 ,  H01L2924/15311 ,  H01L2924/301

Abstract: Methods and apparatuses for balancing current delivery. The method couples a low resistance portion of a ball grid array (BGA) to an input portion by at least two vias forming a three-dimensional section. The method couples at least one ball of the BGA to the low resistance portion over a narrow trace.

Abstract translation: 用于平衡当前交付的方法和装置。 该方法通过形成三维截面的至少两个通孔将球栅阵列（BGA）的低电阻部分耦合到输入部分。 该方法将BGA中的至少一个球与窄电阻部分连接。

公开(公告)号：US20250069965A1

公开(公告)日：2025-02-27

申请号：US18456295

申请日：2023-08-25

Applicant: QUALCOMM Incorporated

Inventor： Ryan LANE ,  Charles David PAYNTER ,  William STONE ,  Ahmer SYED ,  Yue LI ,  Kuiwon KANG ,  Wei WANG ,  Durodami LISK

IPC: H01L23/13 ,  H01L23/00

Abstract: A package comprising an integrated device and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate comprises at least one dielectric layer; a frame at least partially located in the at least one dielectric layer; and a plurality of interconnects located at least partially in the at least one dielectric layer. The frame may be an embedded frame.