PACKAGE COMPRISING A BRIDGE LOCATED BETWEEN METALLIZATION PORTIONS

    公开(公告)号:US20250096207A1

    公开(公告)日:2025-03-20

    申请号:US18470344

    申请日:2023-09-19

    Abstract: A package comprising a first metallization portion; a first integrated device coupled to the first metallization portion; a bridge coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion; a second metallization portion coupled to the bridge and the encapsulation layer, such that the first integrated device, the bridge and the encapsulation layer are located between the first metallization portion and the second metallization portion, and a second integrated device coupled to the second metallization portion, wherein the second integrated device and the bridge at least partially vertically overlap.

    REPURPOSED SEED LAYER FOR HIGH FREQUENCY NOISE CONTROL AND ELECTROSTATIC DISCHARGE CONNECTION

    公开(公告)号:US20210375742A1

    公开(公告)日:2021-12-02

    申请号:US16888516

    申请日:2020-05-29

    Abstract: An integrated circuit (IC) package is described. The IC package includes a die, having a pad layer structure on back-end-of-line layers on a substrate. The die also includes a metallization routing layer on the pad layer structure, and a first under bump metallization layer on the metallization routing layer. The IC package also includes a patterned seed layer on a surface of the die to contact the first under bump metallization layer. The IC package further includes a first package bump on the first under bump metallization layer.

    PACKAGE WITH A SUBSTRATE COMPRISING EMBEDDED STACKED TRENCH CAPACITOR DEVICES

    公开(公告)号:US20240038831A1

    公开(公告)日:2024-02-01

    申请号:US17878758

    申请日:2022-08-01

    CPC classification number: H01L28/91 H01L23/5223 H01L24/16

    Abstract: A package comprising a substrate and an integrated device. The substrate includes a core layer comprising a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, where the second trench capacitor device comprises a second front side and a second back side.

    STACKED EMBEDDED PASSIVE SUBSTRATE STRUCTURE

    公开(公告)号:US20200176417A1

    公开(公告)日:2020-06-04

    申请号:US16209723

    申请日:2018-12-04

    Abstract: The present disclosure generally relates to an integrated circuit having a stacked embedded passive substrate (EPS) structure formed therein. In particular, a substrate may have a cavity formed therein and the stacked EPS structure may include multiple passive components formed in the cavity to provide separate electrical paths for decoupling of the integrated circuit. Furthermore, the multiple passive components may each have two respective terminals such that the multiple passive components may support different voltage domains. Among other things, compared to conventional die-side and/or land-side passive components, the stacked EPS structure may advantageously reduce a z-axis height of the integrated circuit, reduce manufacturing costs, improve performance due to shorter electrical paths, and improve design routing through x-axis and y-axis space savings.

    ANCHORING CONDUCTIVE MATERIAL IN SEMICONDUCTOR DEVICES
    8.
    发明申请
    ANCHORING CONDUCTIVE MATERIAL IN SEMICONDUCTOR DEVICES 审中-公开
    半导体器件中的导电材料

    公开(公告)号:US20170005160A1

    公开(公告)日:2017-01-05

    申请号:US14973479

    申请日:2015-12-17

    CPC classification number: H01L28/60 H01L23/5223 H01L23/53228 H01L28/75

    Abstract: Copper (Cu) grain boundaries can move during a thermal cycle resulting in the Cu grain position being offset. Such Cu pumping can disturb the surface of a bottom metal, and can physically break a dielectric of a metal-insulator-metal (MIM) capacitor. By capping the bottom metal with an anchoring cap, Cu pumping is reduced or eliminated.

    Abstract translation: 铜(Cu)晶界可以在热循环期间移动,导致Cu晶粒位置偏移。 这种Cu泵浦可能会干扰底部金属的表面,并且可以物理地破坏金属 - 绝缘体 - 金属(MIM)电容器的电介质。 通过用锚固帽盖住底部金属,减少或消除Cu泵送。

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