公开(公告)号：US20170336840A1

公开(公告)日：2017-11-23

申请号：US15162452

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206

Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

公开(公告)号：US10394299B2

公开(公告)日：2019-08-27

申请号：US15162371

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/28 ,  G06T1/20 ,  G06F17/50 ,  H01L23/525 ,  H01L23/528 ,  H01L27/118 ,  H01L27/02

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

公开(公告)号：US20170336845A1

公开(公告)日：2017-11-23

申请号：US15162371

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/28 ,  G06T1/20

CPC classification number: G06F1/28 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78 ,  G06T1/20 ,  G06T2200/28 ,  H01L23/525 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2027/11881

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

公开(公告)号：US09958918B2

公开(公告)日：2018-05-01

申请号：US15162452

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/00 ,  G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206

Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.