公开(公告)号：US20170336845A1

公开(公告)日：2017-11-23

申请号：US15162371

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/28 ,  G06T1/20

CPC classification number: G06F1/28 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78 ,  G06T1/20 ,  G06T2200/28 ,  H01L23/525 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2027/11881

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

公开(公告)号：US10394299B2

公开(公告)日：2019-08-27

申请号：US15162371

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/28 ,  G06T1/20 ,  G06F17/50 ,  H01L23/525 ,  H01L23/528 ,  H01L27/118 ,  H01L27/02

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

公开(公告)号：US09958918B2

公开(公告)日：2018-05-01

申请号：US15162452

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/00 ,  G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206

Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

公开(公告)号：US20170336840A1

公开(公告)日：2017-11-23

申请号：US15162452

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206

Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

公开(公告)号：US20150200667A1

公开(公告)日：2015-07-16

申请号：US14155734

申请日：2014-01-15

Applicant: QUALCOMM Incorporated

Inventor： Shiva Ram Chandrasekaran ,  Chandrasekhar Reddy Singasani ,  Joey Dacanay ,  Mamta Bansal ,  Arman Ohanian ,  Satish Raj ,  Kiran Srinivasa Sastry ,  Abhirami Senthilkumaran ,  Tarek Zghal ,  Parissa Najdesamii ,  Sunil Kumar

IPC: H03K19/00 ,  G06F1/32

CPC classification number: H03K19/0008 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

Abstract: Provided are systems and methods for reducing power consumption in the interface and routing circuitry associated with various core modules of an integrated circuit or system. One system includes core modules, glue logic domains adapted to interface the plurality of core modules, and a power controller electrically coupled to the glue logic domains. Each glue logic domain includes a glue logic module implemented as a soft macro with metal traces extending beyond an extent of the glue logic module. The power controller decouples power from selected glue logic domains based on control signals and/or detected power down states of core modules and/or other glue logic domains. The power controller facilitates the power transitions using logic state retention, logic state clamping, ordered or scheduled transitioning, and/or other power transition systems and methods.

Abstract translation: 提供了用于降低与集成电路或系统的各种核心模块相关联的接口和路由电路中的功耗的系统和方法。 一个系统包括核心模块，适于接合多个核心模块的胶合逻辑域，以及电连接到胶合逻辑域的功率控制器。 每个胶合逻辑域包括实现为具有超出胶合逻辑模块的范围的金属迹线的软宏的胶合逻辑模块。 功率控制器基于核心模块和/或其他胶合逻辑域的控制信号和/或检测到的掉电状态来将电力与选定的胶合逻辑域分离。 功率控制器使用逻辑状态保持，逻辑状态钳位，有序或调度转换和/或其他功率转换系统和方法来促进功率转换。