公开(公告)号：US20180307342A1

公开(公告)日：2018-10-25

申请号：US15491877

申请日：2017-04-19

Applicant: QUALCOMM Incorporated

Inventor： Masoud Roham ,  Mishel Matloubian

IPC: G06F3/044 ,  G06K9/00

CPC classification number: G06F3/044 ,  G06K9/0002

Abstract: This disclosure provides systems, methods and apparatus for capacitive touch sensing. In one aspect, a chip seal ring having an integrated capacitive sense plate is provided. In some implementations, a capacitance of the integrated sense plate to a finger may be used to detect the presence of the finger. In some implementations, a fringe capacitance of the seal ring sense plate to the finger is used to detect the presence of the finger. The chip may be sensor chip, for example, a fingerprint sensor chip, and may be implemented in an electronic device.

公开(公告)号：US20210336008A1

公开(公告)日：2021-10-28

申请号：US16857703

申请日：2020-04-24

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet Paul ,  Mishel Matloubian

IPC: H01L29/10 ,  H01L29/66

Abstract: Field-effect transistors (FETs) employing edge transistor current leakage suppression to reduce FET current leakage, and related methods, are disclosed. The FET includes a gate that includes extended-length edge gate regions overlapping semiconductor layer edges to form extended length edge conduction channels in edge transistors. In this manner, the threshold voltage of the edges transistors is increased, thus reducing current leakage of the edges transistors and overall current leakage of the FET. In another aspect, a body connection implant that is formed to short a source or drain region to a body of the FET is extended in length to form body connection implant regions underneath at least a portion of the edge gate regions. In this manner, the work functions of the edge gate regions are increased in voltage thus increasing the threshold voltage of the edge transistors and reducing current leakage of the edges transistors and the FET.

公开(公告)号：US11682632B2

公开(公告)日：2023-06-20

申请号：US17002643

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet Paul ,  Mishel Matloubian

IPC: H01L23/00 ,  H01L21/74 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L21/74 ,  H01L23/585

Abstract: An integrated device that includes a substrate, a circuit region located over the substrate, a design keep out region located over the substrate, and a periphery structure located over the substrate. The design keep out region laterally surrounds the circuit region. The periphery structure includes a first plurality of interconnects that laterally surrounds the design keep out region. The periphery structure is configured to operate as an electrical seal ring and a mechanical crack stop.

公开(公告)号：US11948978B2

公开(公告)日：2024-04-02

申请号：US16857703

申请日：2020-04-24

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet Paul ,  Mishel Matloubian

IPC: H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/1041 ,  H01L29/66477

Abstract: Field-effect transistors (FETs) employing edge transistor current leakage suppression to reduce FET current leakage, and related methods, are disclosed. The FET includes a gate that includes extended-length edge gate regions overlapping semiconductor layer edges to form extended length edge conduction channels in edge transistors. In this manner, the threshold voltage of the edges transistors is increased, thus reducing current leakage of the edges transistors and overall current leakage of the FET. In another aspect, a body connection implant that is formed to short a source or drain region to a body of the FET is extended in length to form body connection implant regions underneath at least a portion of the edge gate regions. In this manner, the work functions of the edge gate regions are increased in voltage thus increasing the threshold voltage of the edge transistors and reducing current leakage of the edges transistors and the FET.

公开(公告)号：US12228538B2

公开(公告)日：2025-02-18

申请号：US18189494

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet Paul ,  Mishel Matloubian

IPC: G01N27/22

Abstract: In an aspect, a device includes: a first patterned metal layer; a first dielectric layer disposed over the first patterned metal layer; a second patterned metal layer disposed over the first dielectric layer, wherein the first patterned metal layer, the first dielectric layer, and the second patterned metal layer form a first capacitor; a second moisture-sensitive dielectric layer disposed over the second patterned metal layer; and a third patterned metal layer disposed over the second moisture-sensitive dielectric layer, wherein the third patterned metal layer, the second moisture-sensitive dielectric layer, and the second patterned metal layer form a second capacitor that is moisture-sensitive, and the first patterned metal layer is further configured as a heating element to assist in removing moisture from the second moisture-sensitive dielectric layer of the second capacitor in response to provision of an electrical power to the first patterned metal layer.