公开(公告)号：US20170352649A1

公开(公告)日：2017-12-07

申请号：US15174684

申请日：2016-06-06

Applicant: QUALCOMM Incorporated

Inventor： Harshat PANT ,  Mohammed Yousuff SHARIFF ,  Parissa NAJDESAMII ,  Ramaprasath VILANGUDIPITCHAI ,  Divjyot BHAN

IPC: H01L27/02 ,  H01L27/088 ,  H01L23/535

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/823892 ,  H01L23/535 ,  H01L27/0886

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.