公开(公告)号：US20250150080A1

公开(公告)日：2025-05-08

申请号：US18504062

申请日：2023-11-07

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath VILANGUDIPITCHAI ,  Venkat NARAYANAN ,  Giby SAMSON ,  Venugopal BOYNAPALLI

IPC: H03K19/0185 ,  H03K3/012 ,  H03K3/356

Abstract: At least one integrated power management cell of an IC includes a first cell, which is a 4-height cell, that includes a first continuous n-well, a first power interconnect coupled to a first voltage source associated with a first voltage domain and to the first continuous n-well, a second continuous n-well, a second power interconnect coupled to a second voltage source associated with a second voltage domain and to the second continuous n-well, a first subset of a first voltage level shifter associated with the first voltage domain and coupled to the first power interconnect, and a second subset of the first voltage level shifter associated with the second voltage domain and coupled to the second power interconnect.

公开(公告)号：US20210058076A1

公开(公告)日：2021-02-25

申请号：US16548517

申请日：2019-08-22

Applicant: QUALCOMM Incorporated

Inventor： Andi ZHAO ,  Ramaprasath VILANGUDIPITCHAI ,  Hyeokjin LIM ,  Seung Hyuk KANG

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/037

Abstract: A hybrid fin flip flop circuit may comprise a mixture of 1-fin transistors and multi-fin transistors. In one example, a flip flop circuit may comprise 1-fin transistors in at least one of the critical paths of the flip flop circuit such as the drive circuit, the input circuit, or the output circuit. In one example, a flip flop circuit may include: an input circuit; a clock driver circuit; an output circuit; and a latch circuit; wherein one of the input circuit, the clock driver circuit, or the output circuit comprises a multi-fin transistor and the latch circuit comprises a plurality of 1-fin transistors.

公开(公告)号：US20200341537A1

公开(公告)日：2020-10-29

申请号：US16395705

申请日：2019-04-26

Applicant: QUALCOMM Incorporated

Inventor： Giby SAMSON ,  Ramaprasath VILANGUDIPITCHAI ,  Seung Hyuk KANG ,  Eunjoo HWANG ,  Hai ZHU ,  Divjyot BHAN

IPC: G06F1/3296 ,  G06F1/28

Abstract: In certain aspects, a system comprises a power collapsible logic block, a plurality of retention flip-flops coupled to the power collapsible logic blocks, wherein the plurality of retention flip-flops includes a group of master-slave flip-flops and a group of balloon flip-flops, and a power controller configured to retain states of the group of balloon flip-flops and states of the group of master-slave flip-flops in a first sleep state and to retain the states of the group of balloon flip-flops but not states of the group of master-slave flip-flops in a deep sleep state.

公开(公告)号：US20230221789A1

公开(公告)日：2023-07-13

申请号：US18000319

申请日：2021-07-28

Applicant: QUALCOMM Incorporated

Inventor： Giby SAMSON ,  Smeeta HEGGOND ,  Jitu Khushalbhai MISTRY ,  Paras GUPTA ,  Keyurkumar Karsanbhai KANSAGRA ,  Kamesh MEDISETTI ,  Ramaprasath VILANGUDIPITCHAI ,  Arshath SHEEPARAMATTI

IPC: G06F1/3296 ,  G06F1/26 ,  G06F1/3234

CPC classification number: G06F1/3296 ,  G06F1/263 ,  G06F1/3275

Abstract: A system on chip (SOC) comprising: first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexor disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide an operating voltage to both the first memory block and the second memory block; and enable logic circuitry disposed at a periphery of the SOC away from the first memory block and the second memory block, the enable logic being coupled to control terminals of the first power multiplexor.

公开(公告)号：US20150262936A1

公开(公告)日：2015-09-17

申请号：US14645336

申请日：2015-03-11

Applicant: QUALCOMM Incorporated

Inventor： Mamta BANSAL ,  Uday DODDANNAGARI ,  Paras GUPTA ,  Ramaprasath VILANGUDIPITCHAI ,  Parissa NAJDESAMII ,  Dorav KUMAR ,  Nitin PARTANI

IPC: H01L23/538 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H04W72/0453 ,  Y02D70/00 ,  H01L2924/00

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract translation: MOS器件包括多个标准单元，其被配置为减少路由拥塞，同时在MOS器件上提供区域节省。 标准细胞可以是共享与其他附近n型孔分离的n型井的单高度标准细胞。 单个高度标准单元的输入和输出信号引脚可以配置在最低可能的金属层（例如，M1）中，而单高度标准单元的次级电源引脚可以配置在较高的金属层（例如，M2 ）。 为次级电源引脚供电的互连可以沿着垂直轨道配置，并在不同的标准单元组之间共享，这可以减少在MOS器件中使用的垂直轨道的数量。 MOS器件中可用的水平路由轨迹的数量可能不受影响，因为主电源/接地网格已经使用的水平轨迹用于电源连接。

公开(公告)号：US20240250669A1

公开(公告)日：2024-07-25

申请号：US18156975

申请日：2023-01-19

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath VILANGUDIPITCHAI ,  Rui CHEN ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC: H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/012

Abstract: A hybrid flop tray, including: a set of flip-flops cascaded along a scan path, wherein a first subset of one or more of the flip-flops of the set includes fin field effect transistors (FinFETs) each sized with a first number of fins, and a second subset of one or more of the flip-flops of the set includes FinFETs each sized with a second number of fins, wherein the first number of fins is different than the second number of fins; and a control circuit configured to provide control signals to the set of flip-flops.

公开(公告)号：US20210391249A1

公开(公告)日：2021-12-16

申请号：US17081720

申请日：2020-10-27

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath VILANGUDIPITCHAI ,  Gudoor REDDY ,  Samrat SINHAROY ,  Smeeta HEGGOND ,  Anil Kumar KODURU ,  Kamesh MEDISETTI ,  Seung Hyuk KANG

IPC: H01L23/522 ,  H01L27/02

Abstract: A cell on an IC includes a first set of Mx layer interconnects coupled to a first voltage, a second set of Mx layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mx layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mx layer interconnects is coupled to the CTM. The second set of Mx layer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mx layer and an Mx-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.

公开(公告)号：US20180145071A1

公开(公告)日：2018-05-24

申请号：US15360777

申请日：2016-11-23

Applicant: QUALCOMM Incorporated

Inventor： Andi ZHAO ,  Ramaprasath VILANGUDIPITCHAI ,  Dorav KUMAR

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H03K17/16

CPC classification number: H01L27/088 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/94 ,  H03K17/162

Abstract: A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled to other pMOS transistor gates. Each pMOS transistor source/drain are coupled to a first voltage source. The MOS IC further includes a first metal interconnect extending over the pMOS transistors. The first metal interconnect has first and second ends. The first metal interconnect is coupled to each pMOS transistor gate and is coupled to a second voltage source less than the first voltage source. One of each pMOS transistor gate or the second voltage source is coupled to the first metal interconnect through at least one tap point located between the first and second ends. The pMOS transistors and the first metal interconnect function as a decoupling capacitor.

公开(公告)号：US20240322819A1

公开(公告)日：2024-09-26

申请号：US18188656

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Giby SAMSON ,  Ramaprasath VILANGUDIPITCHAI ,  Pavan Kumar PATIBANDA ,  Joshua ONG ,  Chethan SWAMYNATHAN ,  Vajram GHANTASALA ,  Venugopal BOYNAPALLI ,  Madan KRISHNAPPA ,  Vineet OORAMKUMARATH ,  Mohamed Saud MUSLIYARAKATH

IPC: H03K17/687 ,  H03K3/012 ,  H03K3/3562

CPC classification number: H03K17/6872 ,  H03K3/012 ,  H03K3/35625

Abstract: Aspects of the present disclosure provide cells including integrated switches and/or integrated clamps. In some aspects, a cell includes a circuit having an input and an output, and a switch coupled between a supply rail and the circuit, wherein the switch is configured to receive an enable signal, turn on when the enable signal has a first logic value, and turn off when the enable signal has a second logic value. The cell also includes a first clamp coupled to the output of the circuit, wherein the first clamp is configured to clamp the output of the circuit when the enable signal has the second logic value.

公开(公告)号：US20210110267A1

公开(公告)日：2021-04-15

申请号：US16599306

申请日：2019-10-11

Applicant: QUALCOMM Incorporated

Inventor： Giby SAMSON ,  Srivatsan CHELLAPPA ,  Ramaprasath VILANGUDIPITCHAI ,  Seung Hyuk KANG

IPC: G06N3/08 ,  G06N3/063 ,  G06F7/544

Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for configuring a multiply-accumulate (MAC) block in an artificial neural network. A method generally includes receiving, at a neural processing unit comprising one or more logic elements, at least one input associated with a use-case of the neural processing unit; obtaining a set of weights associated with the at least one input; selecting a precision for the set of weights; modifying the set of weights based on the selected precision; and generating an output based, at least in part, on the at least one input, the modified set of weights, and an activation function.