公开(公告)号：US20190391608A1

公开(公告)日：2019-12-26

申请号：US16016410

申请日：2018-06-22

Applicant: QUALCOMM Incorporated

Inventor： Lipeng CAO ,  Rajeev JAIN ,  Harshat PANT ,  Byron Glenn MURPHY

IPC: G05F1/59

Abstract: A power multiplexer system including a power mux controller, wherein the power mux controller generates at least one non-regulated control signal; a regulator coupled to the power mux controller, wherein the regulator generates a reference voltage and wherein the reference voltage is used for generating a regulated control signal; and at least one power multiplexer tile coupled to the regulator, wherein each of the at least one power multiplexer tile includes a first branch comprising a first plurality of transistors and a second branch comprising a second plurality of transistors, and wherein enabling or disabling one or more of the first plurality of transistors is based on either the at least one non-regulated control signal or the regulated control signal.

公开(公告)号：US20170352649A1

公开(公告)日：2017-12-07

申请号：US15174684

申请日：2016-06-06

Applicant: QUALCOMM Incorporated

Inventor： Harshat PANT ,  Mohammed Yousuff SHARIFF ,  Parissa NAJDESAMII ,  Ramaprasath VILANGUDIPITCHAI ,  Divjyot BHAN

IPC: H01L27/02 ,  H01L27/088 ,  H01L23/535

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/823892 ,  H01L23/535 ,  H01L27/0886

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.

公开(公告)号：US20240429908A1

公开(公告)日：2024-12-26

申请号：US18340449

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Harshat PANT ,  Hanil LEE ,  Shih-Hsin Jason HU ,  Chulmin JUNG ,  Xiao CHEN ,  Christol BARNES

IPC: H03K17/00 ,  G05F1/46

Abstract: A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.

公开(公告)号：US20230421156A1

公开(公告)日：2023-12-28

申请号：US17849469

申请日：2022-06-24

Applicant: QUALCOMM Incorporated

Inventor： Basma HAJRI ,  Harshat PANT ,  Chirag AGRAWAL ,  Shih-Hsin Jason HU

IPC: H03K19/0948 ,  H03K5/01 ,  H03K19/20

CPC classification number: H03K19/0948 ,  H03K5/01 ,  H03K19/20 ,  H03K2005/00013

Abstract: An aspect relates to a glitch absorbing buffer (GABUF) including: a delay element configured to delay an input signal by a delay to generate a delayed input signal; and a logic circuit, responsive to the input signal, the delayed input signal, and an output signal, configured to propagate a pulse in the input signal to the output signal if a width of the pulse is greater than the delay, and suppress the propagating of the pulse to the output signal if the width of the pulse is less than the delay.