公开(公告)号：US11907154B2

公开(公告)日：2024-02-20

申请号：US17861886

申请日：2022-07-11

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Francesco Gatta ,  Muhlis Kenan Ozel ,  Richard Dominic Wietfeldt

IPC: G06F13/40 ,  H04L7/00 ,  H04L7/04

CPC classification number: G06F13/4068 ,  H04L7/0066 ,  H04L7/0087 ,  H04L7/042 ,  G06F2213/40

Abstract: A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.