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公开(公告)号：US20170288924A1
公开(公告)日：2017-10-05
申请号：US15513889
申请日：2015-07-31
发明人： Aki KAIZU , Masataka IMAO , Eiji MATSUO
CPC分类号： H04L27/22 , H03L7/08 , H04B1/0007 , H04L7/0066 , H04L7/04 , H04L25/49
摘要： A receiving device includes: a receiver that receives a signal including PPM symbols; a clock generator that generates a clock for sampling; an A/D converter that digital-converts the received signal; a reference position detector that detects a leading position of the PPM symbols based on data from the A/D converter; and a clock error detector that detects a clock error. The clock error detector includes: a pulse position detector that detects a pulse position in the PPM symbols based on data from the reference position detector and A/D converter; a position error calculator that calculates a deviation of the pulse position based on data from the reference position detector, A/D converter, and pulse position detector; and a clock error calculator that calculates the clock error based on data from the position error calculator. The receiving device varies a frequency of the clock based on data from the clock error calculator.
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公开(公告)号：US09490967B1
公开(公告)日：2016-11-08
申请号：US14978363
申请日：2015-12-22
发明人： Robert Floyd Payne
CPC分类号： H04L25/0272 , G06F13/38 , H04L1/0045 , H04L7/0008 , H04L7/0066 , H04L25/4917
摘要： A communication system includes a receiver for decoding data having three states of −1, 0, and 1. The receiver includes a first input coupled to a first data line, a second input coupled to a second data line, and a third input coupled to a third data line. A first comparator is coupled to a first output, wherein the first comparator is for generating data signals in response to the sign of voltages on the first data line minus voltages on the second data line. A second comparator is coupled to a second output, wherein the second comparator is for generating clock signals in response to the sign of voltages on the third data line minus the average of voltages on the first and second data lines.
摘要翻译： 通信系统包括用于解码具有三个状态-1,0和1的数据的接收器。接收机包括耦合到第一数据线的第一输入，耦合到第二数据线的第二输入和耦合到第二数据线的第三输入 第三条数据线。 第一比较器耦合到第一输出，其中第一比较器用于响应于第一数据线上的电压的符号减去第二数据线上的电压来产生数据信号。 第二比较器耦合到第二输出，其中第二比较器用于响应于第三数据线上的电压的符号减去第一和第二数据线上的电压的平均来产生时钟信号。
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3.发明申请公开(公告)号：US20160127121A1
公开(公告)日：2016-05-05
申请号：US14992450
申请日：2016-01-11
IPC分类号： H04L7/027 , H04L25/493 , H04L25/02
CPC分类号： H04L7/033 , H03K5/1252 , H03K5/1534 , H04L7/0066 , H04L7/027 , H04L25/0272 , H04L25/14 , H04L25/49 , H04L25/4906 , H04L25/493
摘要： A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential number from a set of sequential numbers. The sequential number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.
摘要翻译： 提供了一种用于执行多线信令编码的方法，其中在符号转换内对时钟信号进行编码。 数据位序列被转换成多个m个转换数。 每个转换号码都从一组连续号码转换为一个顺序号码。 顺序号被转换成可以通过多个差分驱动器发送的原始符号。 原始符号被传播分散在多条n线上，其中时钟信号被有效地嵌入在原始符号的传输中，因为从转换数转换为序列号可保证没有两个连续的原始符号相同。 原始符号保证在多条n线的所有对上具有非零差分电压。
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4.发明申请公开(公告)号：US20160065357A1
公开(公告)日：2016-03-03
申请号：US14939692
申请日：2015-11-12
发明人： Shoichiro Sengoku
CPC分类号： H04L7/0008 , H04L7/0066 , H04L7/0087 , H04L7/0331 , H04L25/0272
摘要： System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multilane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link.
摘要翻译： 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 从在多通道接口的第一通道上发送的第一符号序列提取的时钟用于接收和解码第一符号序列，并且接收和解码在多路接口的第二通道上发送的数据和/或符号 。 时钟信号可以从第一符号序列中的连续符号对之间的N条线路的信令状态的转换导出。 第一条车道可以使用N！ 编码和第二个通道可能是串行或N！ 链接。
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公开(公告)号：US09077505B2
公开(公告)日：2015-07-07
申请号：US13942723
申请日：2013-07-16
发明人： Chih-Chao Yang , Wei-Ying Tu , Yu-Hsun Peng , Feng-Jung Kuo , Chien-Yu Chen
CPC分类号： H04L7/0066 , G09G2330/06 , G09G2370/10
摘要： A signal receiving apparatus and method adapted for receiving a MIPI signal are disclosed. The signal receiving apparatus includes a signal receiver, a selector, a decoding apparatus and a byte boundary searcher. The signal receiver receives a clock signal, and obtains an input data stream according to the clock signal. The selector outputs the input data stream to a first or second output terminal according to a decoding error signal. The byte boundary searcher operates a boundary searching operation on the input data stream for generating a byte tuning information, wherein, the signal receiver adjusts the clock according to the byte tuning information for adjusting the input data stream.
摘要翻译： 公开了一种适于接收MIPI信号的信号接收装置和方法。 信号接收装置包括信号接收器，选择器，解码装置和字节边界搜索器。 信号接收器接收时钟信号，并根据时钟信号获得输入数据流。 选择器根据解码错误信号将输入数据流输出到第一或第二输出端。 字节边界搜索器对输入数据流进行边界搜索操作，以产生字节调谐信息，其中信号接收机根据用于调整输入数据流的字节调谐信息来调整时钟。
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公开(公告)号：US20140368667A1
公开(公告)日：2014-12-18
申请号：US14142848
申请日：2013-12-29
申请人： Intel Corporation
IPC分类号： H04N17/00
CPC分类号： H04N17/002 , G06F13/4278 , H04L7/0066 , H04L7/10 , H04N5/23203
摘要： Apparatus, methods, and systems are herein described for providing a method for calibrating a channel by employing a training sequence during at least one blanking interval. In one embodiment, an apparatus includes a first control logic to send a command to generate a predetermined data pattern during at least one blanking interval. In addition, the apparatus includes a second control logic to determine whether a received data pattern matches the predetermined data pattern.
摘要翻译： 本文描述的装置，方法和系统用于提供一种通过在至少一个消隐间隔期间采用训练序列校准信道的方法。 在一个实施例中，一种装置包括第一控制逻辑，用于在至少一个消隐间隔期间发送命令以产生预定的数据模式。 另外，该装置包括用于确定接收到的数据模式是否与预定数据模式匹配的第二控制逻辑。
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公开(公告)号：US08855248B2
公开(公告)日：2014-10-07
申请号：US13281052
申请日：2011-10-25
申请人： Craig Barner
发明人： Craig Barner
CPC分类号： H04L1/0091 , G06F2207/025 , H03K5/19 , H03K19/20 , H04B1/16 , H04L7/0066 , H04L25/4908
摘要： In an embodiment, a method for determining a word boundary in an incoming data stream includes initializing an N bit register with initial content, receiving a number of consecutive N bit words of the incoming data stream and processing each of the number of consecutive N bit words. The processing includes performing operations per bit position of the register, including performing an XOR operation on a corresponding received data bit and a next received data bit, performing an AND operation on a current state of the bit position of the register and a result of the XOR operation, and storing a result of the AND operation to update the state of the bit position of the register. The word boundary is defined based on the content of the register following the processing of the number of consecutive N bit words.
摘要翻译： 在一个实施例中，一种用于确定输入数据流中的字边界的方法包括：初始化具有初始内容的N位寄存器，接收输入数据流的连续N位字数，并处理多个连续N位字中的每一个 。 该处理包括对寄存器的每位位置执行操作，包括对对应的接收数据位和下一个接收数据位执行异或运算，对寄存器的位位置的当前状态执行与运算， 并且存储AND操作的结果以更新寄存器的位位置的状态。 在处理连续的N位字数之后，基于寄存器的内容来定义字边界。
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8.发明授权Method and apparatus for clock data recovery from Manchester coded serial data stream 有权从曼彻斯特编码串行数据流恢复时钟数据的方法和装置公开(公告)号：US08817933B2
公开(公告)日：2014-08-26
申请号：US13737055
申请日：2013-01-09
申请人： Darshini H. Mehta , Alan Campbell
发明人： Darshini H. Mehta , Alan Campbell
CPC分类号： H04L7/0338 , H04L7/0066 , H04L25/4904
摘要： Methods and apparatus are presented for obtaining clock data from Manchester coded serial data streams, in which received data is sampled at a sample rate higher than the serial data baud rate, multi-bit groups of transition bits are generated which individually indicate data transition locations in a corresponding multi-bit sampled data bit group, and clock data is derived using the multi-bit groups of transition bits without requiring receipt of synchronization data or receipt of a separate clock.
摘要翻译： 提出了用于从曼彻斯特编码串行数据流获得时钟数据的方法和装置，其中接收的数据以高于串行数据波特率的采样率被采样，生成多位转换位组，其分别指示数据转换位置 相应的多位采样数据位组，并且使用转换位的多位组导出时钟数据，而不需要接收同步数据或单独时钟的接收。
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9.发明授权公开(公告)号：US07760835B2
公开(公告)日：2010-07-20
申请号：US10263670
申请日：2002-10-02
CPC分类号： H04L7/0066 , G06K7/0008 , G06K19/0723 , G06K19/07758 , H03K5/135 , H03K5/1565 , H04L7/027
摘要： A wireless communication device includes an antenna configured to receive electromagnetic energy corresponding to a wireless communication signal outputted using an interrogator and to output electrical energy corresponding to the received electromagnetic energy, communication circuitry coupled with the antenna and configured to sample the electrical energy to process the wireless communication signal, synchronization circuitry coupled with the antenna and the communication circuitry and configured to generate a clock signal to control sampling of the electrical energy using the communication circuitry, wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal responsive to a plurality of transitions of the electrical energy during a first data period and wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal during a second data period including generating at least one of the transitions independent of transitions of the electrical energy.
摘要翻译： 无线通信设备包括被配置为接收与使用询问器输出的无线通信信号相对应的电磁能量并且输出与所接收的电磁能量相对应的电能的天线，与天线耦合的通信电路，并被配置为对电能进行采样以处理 无线通信信号，与天线耦合的同步电路和通信电路，并且被配置为产生时钟信号，以使用通信电路来控制电能的采样，其中同步电路被配置为响应于时钟信号中的多个转换 涉及在第一数据周期期间电能的多个转换，并且其中所述同步电路被配置为在第二数据周期期间在所述时钟信号内生成多个转换，包括生成至少一个 的转换独立于电能的转变。
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公开(公告)号：US07515614B1
公开(公告)日：2009-04-07
申请号：US11400222
申请日：2006-04-10
CPC分类号： H04L25/14 , H04L7/0066 , H04L7/033
摘要： A high speed transmission system transfers data streams over a set of data links. Each data link may carry a number of bit streams. A clock signal is not transmitted over the optical link. Instead, an indication of the appropriate clock signal frequency and please is embedded in the transmitted data. At the receiving end, a clock signal of an appropriate frequency and phase is generated. The new clock signal is used to sample and reconstruct the original data streams.
摘要翻译： 高速传输系统通过一组数据链路传输数据流。 每个数据链路可以携带多个比特流。 时钟信号不通过光链路传输。 而是将适当的时钟信号频率的指示嵌入到发送的数据中。 在接收端，产生适当频率和相位的时钟信号。 新的时钟信号用于对原始数据流进行采样和重建。
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