公开(公告)号：US20210020234A1

公开(公告)日：2021-01-21

申请号：US17039845

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Adithya BHASKARAN ,  Mukund NARASIMHAN ,  Shiba Narayan MOHANTY

IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14 ,  G05F3/26

Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.

公开(公告)号：US20210020206A1

公开(公告)日：2021-01-21

申请号：US17039742

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Adithya BHASKARAN ,  Mukund NARASIMHAN ,  Shiba Narayan MOHANTY

IPC: G11C7/06 ,  G11C7/10

Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

公开(公告)号：US20190108872A1

公开(公告)日：2019-04-11

申请号：US15727448

申请日：2017-10-06

Applicant: QUALCOMM Incorporated

Inventor： Sharad Kumar GUPTA ,  Pradeep RAJ ,  Rahul SAHU ,  Mukund NARASIMHAN

IPC: G11C11/419

Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.

公开(公告)号：US20230038670A1

公开(公告)日：2023-02-09

申请号：US17396046

申请日：2021-08-06

Applicant: QUALCOMM Incorporated

Inventor： Mukund NARASIMHAN ,  Murali Krishna ADE ,  Arun David ARUL DIRAVIYAM ,  Mayank GUPTA ,  Boris Dimitrov ANDREEV

IPC: G06F1/10 ,  G06F1/12 ,  G06F9/30 ,  G06F9/54

Abstract: Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.

公开(公告)号：US20180113821A1

公开(公告)日：2018-04-26

申请号：US15461184

申请日：2017-03-16

Applicant: QUALCOMM Incorporated

Inventor： Mukund NARASIMHAN ,  Sharad Kumar GUPTA ,  Dharaneedharan SHANMUGASUNDARAM

IPC: G06F13/16 ,  G11C11/419 ,  G11C11/418 ,  G11C7/10

CPC classification number: G06F13/1689 ,  G11C7/02 ,  G11C7/1087 ,  G11C7/12 ,  G11C11/418 ,  G11C11/419 ,  G11C2207/2209 ,  G11C2207/2245

Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.