公开(公告)号：US09483600B2

公开(公告)日：2016-11-01

申请号：US14645336

申请日：2015-03-11

Applicant: QUALCOMM Incorporated

Inventor： Mamta Bansal ,  Uday Doddannagari ,  Paras Gupta ,  Ramaprasath Vilangudipitchai ,  Parissa Najdesamii ,  Dorav Kumar ,  Nitin Partani

IPC: H01L25/00 ,  G06F17/50 ,  H01L27/02 ,  H04W72/04 ,  H01L23/528 ,  H01L27/092

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H04W72/0453 ,  Y02D70/00 ,  H01L2924/00

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract translation: MOS器件包括多个标准单元，其被配置为减少路由拥塞，同时在MOS器件上提供区域节省。 标准细胞可以是共享与其他附近n型孔分离的n型井的单高度标准细胞。 单个高度标准单元的输入和输出信号引脚可以配置在最低可能的金属层（例如，M1）中，而单高度标准单元的次级电源引脚可以配置在较高的金属层（例如，M2 ）。 为次级电源引脚供电的互连可以沿着垂直轨道配置，并在不同的标准单元组之间共享，这可以减少在MOS器件中使用的垂直轨道的数量。 MOS器件中可用的水平路由轨迹的数量可能不受影响，因为主电源/接地网格已经使用的水平轨迹用于电源连接。