公开(公告)号：US20160248414A1

公开(公告)日：2016-08-25

申请号：US14818114

申请日：2015-08-04

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Dorav Kumar ,  Steven James Dillen ,  Ohsang Kwon ,  Javid Jaffari

IPC: H03K17/042 ,  H03K5/24

CPC classification number: H03K17/04206 ,  H03K5/24 ,  H03K5/26 ,  H03K19/0016

Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

Abstract translation: 本文描述了为电路供电的系统和方法。 在一个实施例中，一种用于上电的方法包括将第一电源轨的电压与第二电源轨的电压进行比较，以及确定第一电源轨的电压是否在第二电源轨的电压的预定量内 至少基于该比较的预定时间段。 该方法还包括在确定第一电源轨的电压在第二电源轨的电压的预定量内至少在预定时间段内的情况下，启动耦合在第一和第二电源轨之间的多个开关的开关 时间。

公开(公告)号：US20170033796A1

公开(公告)日：2017-02-02

申请号：US14814409

申请日：2015-07-30

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Divjyot Bhan ,  Ramaprasath Vilangudipitchai ,  Dorav Kumar

IPC: H03K17/693

CPC classification number: H03K17/693 ,  H03K19/0016

Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.

Abstract translation: 本文公开了一种用于通过电力轨道复用进行电力管理的集成电路（IC）。 在示例方面，IC包括第一电力轨，第二电力轨和负载电力轨。 IC还包括第一组晶体管，其包括耦合到第一电力轨的第一晶体管和包括耦合到第二电力轨的第二晶体管的第二组晶体管。 IC还包括电力多路复用器电路，其被配置为通过顺序地关闭第一组晶体管的第一晶体管，然后顺序地接通第一组晶体管的第一晶体管，从而将负载电源轨从第一电力轨到第二电力轨的电​​力切换 第二组晶体管的第二晶体管。

公开(公告)号：US10459510B1

公开(公告)日：2019-10-29

申请号：US16250953

申请日：2019-01-17

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra Srinivas ,  Uday Shankar Mudigonda ,  Giby Samson ,  Ramaprasath Vilangudipitchai ,  Dorav Kumar

IPC: H03K19/00 ,  H03K17/28 ,  G06F1/32 ,  G06F1/3234 ,  H03K17/693 ,  H03K17/284

Abstract: In certain aspects, an apparatus includes a first plurality of power switch devices. Each of the first plurality of power switch devices includes a delay line having a programmable time delay, and a power switch coupled between a supply rail and a circuit block, wherein the power switch has a control input coupled to the delay line. The apparatus also includes a switch manager configured to program the time delays of the delay lines in the first plurality of power switch devices based on a number of active circuit blocks in a system.

公开(公告)号：US09685940B2

公开(公告)日：2017-06-20

申请号：US14818114

申请日：2015-08-04

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Dorav Kumar ,  Steven James Dillen ,  Ohsang Kwon ,  Javid Jaffari

IPC: H03K17/04 ,  H03K17/042 ,  H03K5/24 ,  H03K19/00 ,  H03K5/26

CPC classification number: H03K17/04206 ,  H03K5/24 ,  H03K5/26 ,  H03K19/0016

Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

公开(公告)号：US09654101B2

公开(公告)日：2017-05-16

申请号：US14814409

申请日：2015-07-30

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Divjyot Bhan ,  Ramaprasath Vilangudipitchai ,  Dorav Kumar

IPC: H03K17/693 ,  H03K19/00

CPC classification number: H03K17/693 ,  H03K19/0016

Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.

公开(公告)号：US10026735B2

公开(公告)日：2018-07-17

申请号：US15360777

申请日：2016-11-23

Applicant: QUALCOMM Incorporated

Inventor： Andi Zhao ,  Ramaprasath Vilangudipitchai ,  Dorav Kumar

IPC: H01L23/522 ,  H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H03K17/16

Abstract: A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled to other pMOS transistor gates. Each pMOS transistor source/drain are coupled to a first voltage source. The MOS IC further includes a first metal interconnect extending over the pMOS transistors. The first metal interconnect has first and second ends. The first metal interconnect is coupled to each pMOS transistor gate and is coupled to a second voltage source less than the first voltage source. One of each pMOS transistor gate or the second voltage source is coupled to the first metal interconnect through at least one tap point located between the first and second ends. The pMOS transistors and the first metal interconnect function as a decoupling capacitor.

公开(公告)号：US09859891B1

公开(公告)日：2018-01-02

申请号：US15192872

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Dorav Kumar ,  Venkatasubramanian Narayanan ,  Bala Krishna Thalla ,  Seid Hadi Rasouli ,  Radhika Vinayak Guttal ,  Sivakumar Paturi

IPC: H03K19/003 ,  H01L27/02 ,  H01L23/528 ,  H01L27/088 ,  H03K19/177

CPC classification number: H03K19/00361 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H03K19/17736 ,  H03K19/17744

Abstract: A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mx layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mx layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a My layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the My layer that is coupled to the second output on the fifth track.

公开(公告)号：US09634026B1

公开(公告)日：2017-04-25

申请号：US15209650

申请日：2016-07-13

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Xiangdong Chen ,  Ramaprasath Vilangudipitchai ,  Dorav Kumar

IPC: H03K19/00 ,  H01L27/11 ,  H01L27/118 ,  H03K19/003 ,  H01L27/02 ,  H01L27/092 ,  H03K19/177

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/0266 ,  H01L27/092 ,  H01L28/00 ,  H01L2027/11875 ,  H03K19/0008 ,  H03K19/00361 ,  H03K19/17728 ,  H03K19/17736

Abstract: A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.

公开(公告)号：US10103626B1

公开(公告)日：2018-10-16

申请号：US15647326

申请日：2017-07-12

Applicant: QUALCOMM Incorporated

Inventor： Venkatasubramanian Narayanan ,  Dorav Kumar ,  Ramaprasath Vilangudipitchai ,  Venugopal Boynapalli

IPC: H02M3/157 ,  H03K17/687 ,  H03K19/173 ,  H02M3/335

Abstract: A power multiplexor includes: a first branch including a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch including a third transistor coupled in series with a fourth transistor between a second power supply and the power output; a controller configured to selectively assert and de-assert a control signal to the first branch and the second branch; a first voltage level shifter coupled between the second transistor and the controller; and a second voltage level shifter coupled between the third transistor and the controller.

公开(公告)号：US09990984B1

公开(公告)日：2018-06-05

申请号：US15370892

申请日：2016-12-06

Applicant: QUALCOMM Incorporated

Inventor： Dorav Kumar ,  Venkat Narayanan ,  Bilal Zafar ,  Seid Hadi Rasouli ,  Venugopal Boynapalli

IPC: G11C11/4094 ,  G11C11/4076 ,  G06F1/12 ,  G06F1/06

CPC classification number: G11C11/4094 ,  G06F1/06 ,  G06F1/12 ,  G06F13/1689 ,  G11C7/222 ,  G11C11/4076

Abstract: The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.