PROGRAMMABLE DISTRIBUTED DATA PROCESSING IN A SERIAL LINK

    公开(公告)号:US20170222685A1

    公开(公告)日:2017-08-03

    申请号:US15420520

    申请日:2017-01-31

    CPC classification number: H04B1/40 H04B17/318 H04L69/323 H04L69/324

    Abstract: A serial transceiver that includes programmable distributed data processing is provided. The serial transceiver can include an ingress channel that receives serial ingress data and an egress channel that transmits serial egress data. The serial transceiver can also include first and second layers that are one and another of a transport layer, a link layer, or a physical layer (PHY). The first and second layers can include elements that process the ingress data and the egress data. The serial transceiver can also include a programmable controller, a first interconnect that connects the programmable controller to the first layer, and a second interconnect that connects the programmable controller to the second layer. The programmable controller can send first data via the first interconnect to the first layer, and the first data can be processed by one of the first layer elements.

    SCALABLE, HIGH-EFFICIENCY, HIGH-SPEED SERIALIZED INTERCONNECT

    公开(公告)号:US20170222686A1

    公开(公告)日:2017-08-03

    申请号:US15420670

    申请日:2017-01-31

    CPC classification number: H04B1/40 H04B17/318 H04L69/323 H04L69/324

    Abstract: Serial communication using a packetization protocol engineered for efficient transmission is provided. Data link layer (DLL) control packets can be generated for transmission of control messages. Each DLL control message packet can have a DLL control packet length, and the DLL control packet length can be a fixed length. Physical layer (PHY) control packets can be generated. Each PHY control packet can include one of the DLL control packets and a control token. The length of each PHY control packet can be the sum of the DLL control packet length and a control token length of the control token. The PHY control packets can be encapsulated in frames. Each of the frames can include a synchronization symbol having a symbol length. The length of each frame can be the sum of the symbol length and an encapsulation length, which can be twice the length of the PHY control packet.

    UNIDIRECTIONAL CLOCK SIGNALING IN A HIGH-SPEED SERIAL LINK

    公开(公告)号:US20170220517A1

    公开(公告)日:2017-08-03

    申请号:US15422263

    申请日:2017-02-01

    Abstract: Transmission of data over a serial link based on a unidirectional clock signal is provided. A unidirectional clock signal is generated based on a first clock of a master device. The unidirectional clock signal is sent to a slave device that is connected to the serial link. The master device transmits data to the slave device over the serial link based on the first clock. The slave device receives the unidirectional clock signal from a master device. The slave device transmits data over the serial link to the master device based on the unidirectional clock signal.

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