公开(公告)号：US20170242070A1

公开(公告)日：2017-08-24

申请号：US15051537

申请日：2016-02-23

Applicant: QUALCOMM Incorporated

Inventor： Paul Giotta ,  Sachin Dasnurkar

IPC: G01R31/30 ,  G01R31/28

CPC classification number: G01R31/30 ,  G01R31/2831 ,  G01R31/2894 ,  G05B19/41875 ,  H01L22/14 ,  H01L22/20

Abstract: Embodiments described herein provide a method for identifying failure patterns in electronic devices. The method begins when a limit is determined for a parameter of interest. A series of the electronic devices is then tested using the limit of the parameter of interest. Failing devices are then identified and x and y coordinate values are plotted. Pattern recognition may be used to determine if the failures shown on the coordinate plot fit a failure pattern. The limit of the parameter of interest is then regressed in steps to the mean value of the failing devices and the electronic devices are retested. The failure pattern of the retested devices is examined to determine if the failure pattern fits a failure pattern. If the failure pattern fits a failure pattern then the parameter of interest may be found to affect the yield rate of production for the electronic devices.