公开(公告)号：US20250053310A1

公开(公告)日：2025-02-13

申请号：US18447159

申请日：2023-08-09

Applicant: QUALCOMM Incorporated

Inventor： Prasad Rao KOLETI ,  Pranav AGRAWAL ,  Vipan Kumar BINDAL ,  Shriharsha CHEBBI ,  Ankith AGARWAL ,  Raja Simha REVANURU

IPC: G06F3/06

Abstract: Various embodiments include methods and devices for implementing scaling memory frequency configuration by a computing device. Embodiments may include comparing at least a memory refresh rate, a memory size, at least one use case bandwidth of transmission between the memory and a system on chip (SoC), and a use case latency of transmission between the memory and the SoC with at least one stored memory refresh rate, at least one stored memory size, at least one stored use case bandwidth of transmission between the memory and the SoC, and at least one stored use case latency of transmission between the memory and the SoC, selecting a memory frequency based on a result of the comparison, and configuring the memory for the memory frequency. Some embodiments may include issuing an alarm indicating changing the use for the memory to be able to achieve a use case parameter.

公开(公告)号：US20240211141A1

公开(公告)日：2024-06-27

申请号：US18145251

申请日：2022-12-22

Applicant: QUALCOMM Incorporated

Inventor： Prathviraj SHETTY ,  Srikar KARNAM VENKAT NAGA ,  Pranav AGRAWAL ,  Pankaj Kumar SHARMA ,  Louis LOUIE ,  Amod KUMAR ,  Shekar Babu MERLA ,  Odelu KUKATLA ,  Ravi Teja MANDAVILLI ,  Anshul VERMA ,  Sampath Kumar KULASEKARA ,  Sudhakar CHAKALI ,  Rajkumar HARIHARAN

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0673

Abstract: Various embodiments include methods for controlling memory utilization to accommodate changes in memory accessibility due to memory refreshes include controlling bandwidth of at least one processor based on a refresh rate of a memory. Some embodiments may include receiving the refresh rate of the memory at a memory controller, and determining whether the refresh rate of the memory violates a high or low memory refresh rate threshold, sending an instruction configured to reduce or restore the bandwidth of the at least one processor in response to the determination. In some embodiments the methods may be performed by a quality of service manager, which may be part of a memory controller.

公开(公告)号：US20230386551A1

公开(公告)日：2023-11-30

申请号：US18249925

申请日：2021-10-20

Applicant: QUALCOMM INCORPORATED

Inventor： Pranav AGRAWAL ,  Akash SUTHAR ,  Aman CHHETRY ,  Kunal DESAI

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/40615

Abstract: A kernel of an HLOS may originate one or more memory refresh requests. Each memory refresh request may have a first memory address range and a size value. A resource power manager may be coupled to the kernel and coupled to memory. The memory may have a plurality of memory ranks. The resource power manger may receive a memory refresh request from the kernel. The resource power manager may then determine if the plurality of memory ranks is either symmetrical or asymmetrical. If the memory ranks are symmetrical, then the resource power manager distributes the memory refresh request evenly and in a parallel manner across the symmetrical memory ranks. If the memory ranks are asymmetrical, then the resource power manager will then determine if the memory refresh request should be one of: a linear only memory refresh; an interleave with linear memory refresh; or an interleave only memory refresh.