公开(公告)号：US20160270018A1

公开(公告)日：2016-09-15

申请号：US15066954

申请日：2016-03-10

Applicant: QUALCOMM Incorporated

Inventor： Linhai HE ,  Rashid Ahmed Akbar ATTAR ,  Bibhu MOHANTY ,  Joseph Binamira SORIAGA ,  Maksim KRASNYANSKIY ,  Yacob COHEN-ARAZI ,  Rajesh KUMAR ,  Ron SCHNEIDER ,  Wenjia LAI

IPC: H04W56/00 ,  H04W74/08 ,  H04W36/30 ,  H04L5/00 ,  H04W74/04 ,  H04W36/38

CPC classification number: H04W56/0025 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0025 ,  H04L5/0007 ,  H04L5/0048 ,  H04L5/0053 ,  H04L27/2655 ,  H04W36/0005 ,  H04W36/30 ,  H04W56/0015 ,  H04W72/1284 ,  H04W74/04 ,  H04W84/12

Abstract: Various aspects are provided for low-latency wireless local area networks (WLANs). An access point (AP) may transmit a downlink pilot signal for synchronization of the AP with one or more wireless stations. The AP may receive an uplink control block synchronized with the downlink pilot signal including a reservation for uplink transmission from a first wireless station of the one or more wireless stations. The reservation may include an uplink pilot signal and a modulated pilot signal and indicate that the first wireless station has traffic for uplink transmission to the AP. The AP may schedule the first wireless station for uplink transmission during a traffic block after the uplink control block. The AP may estimate a wireless channel to the first wireless station based on the pilot signal and the modulated pilot signal. Other low-latency aspects apply to WLANs in which the AP and associated wireless stations are synchronized.

Abstract translation: 为低延迟无线局域网（WLAN）提供了各种方面。 接入点（AP）可以发送用于AP与一个或多个无线站的同步的下行链路导频信号。 AP可以接收与下行链路导频信号同步的上行链路控制块，该上行链路控制块包括来自一个或多个无线站的第一无线站的上行链路传输的预留。 预约可以包括上行链路导频信号和调制的导频信号，并且指示第一无线站具有用于上行链路传输到AP的业务。 AP可以在上行链路控制块之后的业务块期间调度第一无线站用于上行链路传输。 AP可以基于导频信号和调制的导频信号估计到第一无线站的无线信道。 其他低延迟方面适用于AP和相关无线站同步的WLAN。

公开(公告)号：US20190037460A1

公开(公告)日：2019-01-31

申请号：US15662210

申请日：2017-07-27

Applicant: QUALCOMM Incorporated

Inventor： Abhijit BHATTACHARYA ,  Yanjun SUN ,  Peerapol TINNAKORNSRISUPHAP ,  Brian Michael BUESKER ,  Saiyiu Duncan HO ,  Rajesh KUMAR ,  Rohit KAPOOR

IPC: H04W36/08

Abstract: Disclosed are methods and systems for a wireless communication network including detecting a trigger to switch a serving channel at a first access point, and communicating a first channel switch message from the first access point to a second access point. The first access point may be in a downstream and/or upstream or communication flow in relation to the second access point. The process may include communicating a first Channel Switching Announcement (CSA) message from the second access point to at least one client of the second access point, where the least one client is one of a plurality of clients receiving internet connectivity through a series of communication flows including a data flow through the second access point. The process further includes revising a time to switch channel information included in the first channel switch message, where the first CSA message includes the revised time to switch channel information.

公开(公告)号：US20180150394A1

公开(公告)日：2018-05-31

申请号：US15647202

申请日：2017-07-11

Applicant: QUALCOMM Incorporated

Inventor： Ramasamy ADAIKKALAVAN ,  Harish SHANKAR ,  Rajesh KUMAR

IPC: G06F12/0808 ,  G06F17/30 ,  G06F12/1045 ,  G06F12/1009

CPC classification number: G06F12/0808 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1045 ,  G06F16/90339 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2212/68 ,  G11C15/04

Abstract: Systems and methods for cache invalidation, with support for different modes of cache invalidation include receiving a matchline signal, wherein the matchline signal indicates whether there is a match between a search word and an entry of a tag array of the cache. The matchline signal is latched in a latch controlled by a function of a single bit mismatch clock, wherein a rising edge of the single bit mismatch clock is based on delay for determining a single bit mismatch between the search word and the entry of the tag array. An invalidate signal for invalidating a cacheline corresponding to the entry of the tag array is generated at an output of the latch. Circuit complexity is reduced by gating a search word with a search-invalidate signal, such that the gated search word corresponds to the search word for a search-invalidate and to zero for a Flash-invalidate.

公开(公告)号：US20190214076A1

公开(公告)日：2019-07-11

申请号：US16134937

申请日：2018-09-18

Applicant: QUALCOMM Incorporated

Inventor： Harish SHANKAR ,  Manish GARG ,  Rahul Krishnakumar NADKARNI ,  Rajesh KUMAR ,  Michael PHAN

IPC: G11C11/419

Abstract: Disclosed is a memory system comprising a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.