公开(公告)号：US10692808B2

公开(公告)日：2020-06-23

申请号：US15707807

申请日：2017-09-18

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad Hiremath ,  Hyeokjin Lim ,  Foua Vang ,  Xiangdong Chen ,  Venugopal Boynapalli

IPC: H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092

Abstract: In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.

公开(公告)号：US20190088591A1

公开(公告)日：2019-03-21

申请号：US15707807

申请日：2017-09-18

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad Hiremath ,  Hyeokjin Lim ,  Foua Vang ,  Xiangdong Chen ,  Venugopal Boynapalli

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/092

Abstract: In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.