公开(公告)号：US11437379B2

公开(公告)日：2022-09-06

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Deepak Sharma ,  Bharani Chava ,  Hyeokjin Lim ,  Peijie Feng ,  Seung Hyuk Kang ,  Jonghae Kim ,  Periannan Chidambaram ,  Kern Rim ,  Giridhar Nallapati ,  Venugopal Boynapalli ,  Foua Vang

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/095 ,  H01L23/528 ,  H01L29/78 ,  H03K19/0185

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US09053960B2

公开(公告)日：2015-06-09

申请号：US13784811

申请日：2013-03-04

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Mukul Gupta ,  Foua Vang

IPC: H01L27/07 ,  H01L27/08 ,  H01L29/66 ,  H01L27/01 ,  H01L29/94

CPC classification number: H01L27/0811 ,  H01L27/016 ,  H01L29/66181 ,  H01L29/94

Abstract: An integrated circuit includes a capacitor having first, second and third nodes. The first and second nodes of the first transistor are connected together and the first and second nodes of the second transistor are connected together. The third node of the first transistor is connected to the third node of the second transistor. Each of the third nodes is constructed so that each node comprises a width and a length that is at least ten percent of the width.

Abstract translation: 集成电路包括具有第一，第二和第三节点的电容器。 第一晶体管的第一和第二节点连接在一起，第二晶体管的第一和第二节点连接在一起。 第一晶体管的第三节点连接到第二晶体管的第三节点。 每个第三节点被构造成使得每个节点包括宽度和至少占宽度百分之十的长度。

公开(公告)号：US20140124868A1

公开(公告)日：2014-05-08

申请号：US13671114

申请日：2012-11-07

Applicant: QUALCOMM INCORPORATED

Inventor： Pratyush Kamal ,  Esin Terzioglu ,  Foua Vang ,  Prayag Bhanubhai Patel ,  Giridhar Nallapati ,  Animesh Datta

IPC: H01L27/092 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L2027/11831

Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

Abstract translation: 半导体标准单元包括N型扩散区和P型扩散区，两者均延伸穿过电池并且还在电池外部。 电池还包括在每个扩散区域上方的导电栅极以产生半导体器件。 一对虚拟栅极也在N型扩散区域和P型扩散区域之上，形成一对虚设装置。 一对虚拟门设置在电池的相对边缘。 电池还包括第一导线，其被配置为将虚设装置耦合到用于禁用虚设装置的电力。

公开(公告)号：US11710733B2

公开(公告)日：2023-07-25

申请号：US16808336

申请日：2020-03-03

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin Lim ,  Bharani Chava ,  Foua Vang ,  Seung Hyuk Kang ,  Venugopal Boynapalli

IPC: H01L27/02 ,  H03K19/0185 ,  H01L23/528

CPC classification number: H01L27/0207 ,  H01L23/528 ,  H03K19/018557

Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2≤m m*P.

公开(公告)号：US09318476B2

公开(公告)日：2016-04-19

申请号：US14195525

申请日：2014-03-03

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Animesh Datta ,  Seid Hadi Rasouli

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L21/76895 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11831 ,  H01L2027/11861 ,  H01L2027/11866

Abstract: A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain. The cell includes a local interconnect structure that couples the dummy gate and a portion of the OD region adjacent a second opposing side of the dummy gate to a source voltage.

Abstract translation: 提供晶体管单元，其包括覆盖连续氧化物定义（OD）区域的虚拟栅极。 与虚设的第一侧相邻的OD区域的第一部分形成漏极。 单元包括局部互连结构，其将虚拟栅极和邻近伪栅极的第二相对侧的OD区域的一部分耦合到源极电压。

公开(公告)号：US08836040B2

公开(公告)日：2014-09-16

申请号：US13671114

申请日：2012-11-07

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Esin Terzioglu ,  Foua Vang ,  Prayag Bhanubhai Patel ,  Giridhar Nallapati ,  Animesh Datta

IPC: H01L21/70 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/118 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L2027/11831

Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

Abstract translation: 半导体标准单元包括N型扩散区和P型扩散区，两者均延伸穿过电池并且还在电池外部。 电池还包括在每个扩散区域上方的导电栅极以产生半导体器件。 一对虚拟栅极也在N型扩散区域和P型扩散区域的上方，形成一对虚设装置。 一对虚拟门设置在电池的相对边缘。 电池还包括第一导线，其被配置为将虚设装置耦合到用于禁用虚设装置的电力。

公开(公告)号：US20140246715A1

公开(公告)日：2014-09-04

申请号：US13784811

申请日：2013-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： Pratyush Kamal ,  Mukul Gupta ,  Foua Vang

IPC: H01L27/07 ,  H01L21/8234

CPC classification number: H01L27/0811 ,  H01L27/016 ,  H01L29/66181 ,  H01L29/94

Abstract: An integrated circuit includes a capacitor having first, second and third nodes. The first and second nodes of the first transistor are connected together and the first and second nodes of the second transistor are connected together. The third node of the first transistor is connected to the third node of the second transistor. Each of the third nodes is constructed so that each node comprises a width and a length that is at least ten percent of the width.

Abstract translation: 集成电路包括具有第一，第二和第三节点的电容器。 第一晶体管的第一和第二节点连接在一起，第二晶体管的第一和第二节点连接在一起。 第一晶体管的第三节点连接到第二晶体管的第三节点。 每个第三节点被构造成使得每个节点包括宽度和至少占宽度百分之十的长度。

公开(公告)号：US20220102266A1

公开(公告)日：2022-03-31

申请号：US17038098

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin Lim ,  Stanley Seungchul Song ,  Foua Vang ,  Seung Hyuk Kang

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods are disclosed. The circuit includes a front side metal line disposed adjacent to a front side of a semiconductor device for providing front side signal routing. The circuit also includes a back side metal line disposed adjacent to a back side of the semiconductor device for providing back side signal routing. In this manner, the back side area of the semiconductor device may be employed for signal routing to conserve area and/or reduce routing complexity. The circuit also includes a back side-front side connection structure that electrically couples the front side metal line to the back side metal line to support signal routing from the back side to the front side of the circuit, or vice versa to provide greater routing flexibility.

公开(公告)号：US10692808B2

公开(公告)日：2020-06-23

申请号：US15707807

申请日：2017-09-18

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad Hiremath ,  Hyeokjin Lim ,  Foua Vang ,  Xiangdong Chen ,  Venugopal Boynapalli

IPC: H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092

Abstract: In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.

公开(公告)号：US10593700B2

公开(公告)日：2020-03-17

申请号：US15855996

申请日：2017-12-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L27/118 ,  H01L23/535 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.