公开(公告)号：US09384795B1

公开(公告)日：2016-07-05

申请号：US14698843

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： David Paul Hoff ,  Jason Philip Martzloff ,  Robert Andrew Sweitzer

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/106 ,  G11C7/10 ,  G11C7/1009 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C11/419

Abstract: In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read wordline from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.

Abstract translation: 在根据有效/无效状态对每行进行限定的数组中，每行可以包括有效门控读取电路，以有条件地阻止读取字线切换，除非该行存储具有有效状态或读取强制信号的数据字 被断言。 此外，在写入操作中，每行可以具有有效门控写入电路，其有条件地阻止写入字线切换，除非要写入行的输入数据具有有效状态或写入强制信号被断言。 此外，除非要读取的行存储具有有效状态的数据字或读取强制信号被断言，否则输出锁存时钟可能被阻止，并且输入锁存时钟也可能被阻塞，除非要写入的输入数据具有 有效状态或写力信号被断言。