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公开(公告)号：US10725740B2
公开(公告)日：2020-07-28
申请号：US16118162
申请日：2018-08-30
发明人： Mattheus Cornelis Antonius Adrianus Heddes , Robert Dreyer , Colin Beaton Verrilli , Natarajan Vaidhyanathan , Koustav Bhattacharya
摘要： Providing efficient multiplication of sparse matrices in matrix-processor-based devices is disclosed herein. In one aspect, a matrix processor of a matrix-processor-based device includes a plurality of sequencers coupled to a plurality of multiply/accumulate (MAC) units for performing multiplication and accumulation operations. Each sequencer determines whether a product of an element of a first input matrix to be multiplied with an element of a second input matrix has a value of zero (e.g., by determining whether the element of the first input matrix has a value of zero, or by determining whether either the element of the first input matrix or that of the second input matrix has a value of zero). If the product of the elements of the first input matrix and the second input matrix does not have a value of zero, the sequencer provides the elements to a MAC unit to perform a multiplication and accumulation operation.
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公开(公告)号：US10936943B2
公开(公告)日：2021-03-02
申请号：US16117952
申请日：2018-08-30
发明人： Colin Beaton Verrilli , Mattheus Cornelis Antonius Adrianus Heddes , Natarajan Vaidhyanathan , Koustav Bhattacharya , Robert Dreyer
摘要： Providing flexible matrix processors for performing neural network convolution in matrix-processor-based devices is disclosed. In this regard, a matrix-processor-based device provides a central processing unit (CPU) and a matrix processor. The matrix processor reorganizes a plurality of weight matrices and a plurality of input matrices into swizzled weight matrices and swizzled input matrices, respectively, that have regular dimensions natively supported by the matrix processor. The matrix-processor-based device then performs a convolution operation using the matrix processor to perform matrix multiplication/accumulation operations for the regular dimensions of the weight matrices and the input matrices, and further uses the CPU to execute instructions for handling the irregular dimensions of the weight matrices and the input matrices (e.g., by executing a series of nested loops, as a non-limiting example). The matrix-processor-based device thus provides efficient hardware acceleration by taking advantage of dimensional regularity, while maintaining the flexibility to handle different variations of convolution.
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3.发明授权公开(公告)号：US10747501B2
公开(公告)日：2020-08-18
申请号：US16118099
申请日：2018-08-30
发明人： Mattheus Cornelis Antonius Adrianus Heddes , Natarajan Vaidhyanathan , Robert Dreyer , Colin Beaton Verrilli , Koustav Bhattacharya
摘要： Providing efficient floating-point operations using matrix processors in processor-based systems is disclosed. In this regard, a matrix-processor-based device provides a matrix processor comprising a positive partial sum accumulator and a negative partial sum accumulator. As the matrix processor processes pairs of floating-point operands, the matrix processor calculates an intermediate product based on a first floating-point operand and a second floating-point operand and determines a sign of the intermediate product. Based on the sign, the matrix processor normalizes the intermediate product with a partial sum fraction of the positive partial sum accumulator or the negative partial sum accumulator, then adds the intermediate product to the positive sum accumulator or the negative sum accumulator. After processing all pairs of floating-point operands, the matrix processor subtracts the negative partial sum accumulator from the positive partial sum accumulator to generate a final sum, then renormalizes the final sum a single time.
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公开(公告)号：US20190079903A1
公开(公告)日：2019-03-14
申请号：US16129480
申请日：2018-09-12
发明人： Robert Dreyer , Mattheus Cornelis Antonius Adrianus Heddes , Colin Beaton Verrilli , Natarajan Vaidhyanathan , Koustav Bhattacharya
摘要： Providing matrix multiplication using vector registers in processor-based devices is disclosed. In one aspect, a method for providing matrix multiplication comprises rearranging elements of a first submatrix and a second submatrix into first and second vectors, respectively, which are stored in first and second vector registers. A matrix multiplication vector operation using the first and second vector registers as input operands is then performed to generate an output vector that is stored in an output vector register. Each element E of the output vector, where 0≤E
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5.发明申请公开(公告)号：US20190065146A1
公开(公告)日：2019-02-28
申请号：US16118099
申请日：2018-08-30
发明人： Mattheus Cornelis Antonius Adrianus Heddes , Natarajan Vaidhyanathan , Robert Dreyer , Colin Beaton Verrilli , Koustav Bhattacharya
摘要： Providing efficient floating-point operations using matrix processors in processor-based systems is disclosed. In this regard, a matrix-processor-based device provides a matrix processor comprising a positive partial sum accumulator and a negative partial sum accumulator. As the matrix processor processes pairs of floating-point operands, the matrix processor calculates an intermediate product based on a first floating-point operand and a second floating-point operand and determines a sign of the intermediate product. Based on the sign, the matrix processor normalizes the intermediate product with a partial sum fraction of the positive partial sum accumulator or the negative partial sum accumulator, then adds the intermediate product to the positive sum accumulator or the negative sum accumulator. After processing all pairs of floating-point operands, the matrix processor subtracts the negative partial sum accumulator from the positive partial sum accumulator to generate a final sum, then renormalizes the final sum a single time.
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6.发明申请公开(公告)号：US20190065942A1
公开(公告)日：2019-02-28
申请号：US16117952
申请日：2018-08-30
发明人： Colin Beaton Verrilli , Mattheus Cornelis Antonius Adrianus Heddes , Natarajan Vaidhyanathan , Koustav Bhattacharya , Robert Dreyer
摘要： Providing flexible matrix processors for performing neural network convolution in matrix-processor-based devices is disclosed. In this regard, a matrix-processor-based device provides a central processing unit (CPU) and a matrix processor. The matrix processor reorganizes a plurality of weight matrices and a plurality of input matrices into swizzled weight matrices and swizzled input matrices, respectively, that have regular dimensions natively supported by the matrix processor. The matrix-processor-based device then performs a convolution operation using the matrix processor to perform matrix multiplication/accumulation operations for the regular dimensions of the weight matrices and the input matrices, and further uses the CPU to execute instructions for handling the irregular dimensions of the weight matrices and the input matrices (e.g., by executing a series of nested loops, as a non-limiting example). The matrix-processor-based device thus provides efficient hardware acceleration by taking advantage of dimensional regularity, while maintaining the flexibility to handle different variations of convolution.
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7.发明申请公开(公告)号：US20190065150A1
公开(公告)日：2019-02-28
申请号：US16118162
申请日：2018-08-30
发明人： Mattheus Cornelis Antonius Adrianus Heddes , Robert Dreyer , Colin Beaton Verrilli , Natarajan Vaidhyanathan , Koustav Bhattacharya
摘要： Providing efficient multiplication of sparse matrices in matrix-processor-based devices is disclosed herein. In one aspect, a matrix processor of a matrix-processor-based device includes a plurality of sequencers coupled to a plurality of multiply/accumulate (MAC) units for performing multiplication and accumulation operations. Each sequencer determines whether a product of an element of a first input matrix to be multiplied with an element of a second input matrix has a value of zero (e.g., by determining whether the element of the first input matrix has a value of zero, or by determining whether either the element of the first input matrix or that of the second input matrix has a value of zero). If the product of the elements of the first input matrix and the second input matrix does not have a value of zero, the sequencer provides the elements to a MAC unit to perform a multiplication and accumulation operation.
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