公开(公告)号：US12261612B2

公开(公告)日：2025-03-25

申请号：US18177445

申请日：2023-03-02

Applicant: QUALCOMM Incorporated

Inventor： John Abcarius ,  Debesh Bhatta ,  Andrew Weil ,  Robert Martin Ondris ,  Wenjing Yin

IPC: H03L7/099

Abstract: Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.