公开(公告)号：US11614763B1

公开(公告)日：2023-03-28

申请号：US17568614

申请日：2022-01-04

Applicant: QUALCOMM Incorporated

Inventor： Debesh Bhatta ,  Sulin Li ,  Shitong Zhao ,  Hui Wang ,  John Abcarius

IPC: G05F3/26 ,  G05F1/46

Abstract: An aspect of the disclosure relates to a reference voltage generator, including: a first field effect transistor (FET) including a first threshold voltage; a second FET including a second threshold voltage different than the first threshold voltage; a gate voltage generator coupled to gates of the first and second FETs; a first current source coupled in series with the first FET between first and second voltage rails; a second current source; and a first resistor coupled in series with the second current source and the second FET between the first and second voltage rails, wherein a reference voltage is generated across the first resistor.

公开(公告)号：US10447282B2

公开(公告)日：2019-10-15

申请号：US15863672

申请日：2018-01-05

Applicant: QUALCOMM Incorporated

Inventor： John Abcarius

IPC: H03L7/089 ,  H03L7/093 ,  H04L27/152 ,  H04L27/148

Abstract: A phase locked loop (PLL) includes a first charge pump coupled to a filter. The first charge pump may feed the filter a first current. A second charge pump is coupled to the filter. The second charge pump may feed the filter a second current. A first gate is coupled to an input of the second charge pump. The first gate selectively gates the second current.

公开(公告)号：US12261612B2

公开(公告)日：2025-03-25

申请号：US18177445

申请日：2023-03-02

Applicant: QUALCOMM Incorporated

Inventor： John Abcarius ,  Debesh Bhatta ,  Andrew Weil ,  Robert Martin Ondris ,  Wenjing Yin

IPC: H03L7/099

Abstract: Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

公开(公告)号：US10958279B1

公开(公告)日：2021-03-23

申请号：US16563083

申请日：2019-09-06

Applicant: QUALCOMM Incorporated

Inventor： Debesh Bhatta ,  Kevin Jia-Nong Wang ,  Karthik Nagarajan ,  John Abcarius ,  Andrew Weil ,  Christian Venerus ,  Jeffrey Mark Hinrichs

IPC: H03M1/66 ,  H03M1/06 ,  H03C3/09 ,  H03M1/70

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.