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    Reference voltage generator based on threshold voltage difference of field effect transistors
    2.
    发明授权
    Reference voltage generator based on threshold voltage difference of field effect transistors 有权

    公开(公告)号：US11614763B1

    公开(公告)日：2023-03-28

    申请号：US17568614

    申请日：2022-01-04

    Applicant: QUALCOMM Incorporated

    Inventor： Debesh Bhatta ,  Sulin Li ,  Shitong Zhao ,  Hui Wang ,  John Abcarius

    IPC: G05F3/26 ,  G05F1/46

    Abstract: An aspect of the disclosure relates to a reference voltage generator, including: a first field effect transistor (FET) including a first threshold voltage; a second FET including a second threshold voltage different than the first threshold voltage; a gate voltage generator coupled to gates of the first and second FETs; a first current source coupled in series with the first FET between first and second voltage rails; a second current source; and a first resistor coupled in series with the second current source and the second FET between the first and second voltage rails, wherein a reference voltage is generated across the first resistor.

    High impedance passive switched capacitor common mode feedback network
    4.
    发明授权
    High impedance passive switched capacitor common mode feedback network 有权

    公开(公告)号：US10122370B2

    公开(公告)日：2018-11-06

    申请号：US15447680

    申请日：2017-03-02

    Applicant: QUALCOMM Incorporated

    Inventor： Debesh Bhatta ,  Jeffrey Mark Hinrichs ,  Wenjing Yin

    IPC: H03L7/089 ,  H03L7/23 ,  H03G1/00

    Abstract: A switched capacitor circuit includes a first capacitor coupled in series with a second capacitor in a first mode of operation across differential output terminals of a circuit. The first capacitor and the second capacitor are coupled in an anti-parallel layout in a second mode of operation. The switched capacitor circuit also includes a third capacitor coupled on a first side to a common node of the first capacitor and the second capacitor. The third capacitor is further coupled on a second side to a current source control voltage in the first mode of operation, and coupled between a bias reference voltage and a common mode reference voltage in the second mode of operation.

    Compact frequency-locked loop architecture for digital clocking
    8.
    发明授权
    Compact frequency-locked loop architecture for digital clocking 有权

    公开(公告)号：US12261612B2

    公开(公告)日：2025-03-25

    申请号：US18177445

    申请日：2023-03-02

    Applicant: QUALCOMM Incorporated

    Inventor： John Abcarius ,  Debesh Bhatta ,  Andrew Weil ,  Robert Martin Ondris ,  Wenjing Yin

    IPC: H03L7/099

    Abstract: Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

    Resistor-capacitor oscillator (RCO) with digital calibration and quantizaton noise reduction
    9.
    发明授权
    Resistor-capacitor oscillator (RCO) with digital calibration and quantizaton noise reduction 有权

    公开(公告)号：US11115036B1

    公开(公告)日：2021-09-07

    申请号：US16991882

    申请日：2020-08-12

    Applicant: QUALCOMM Incorporated

    Inventor： Shitong Zhao ,  Kevin Jia-Nong Wang ,  Shyam Sivakumar ,  Debesh Bhatta

    IPC: H03L7/093 ,  H03L7/099 ,  H03L7/24 ,  H03L7/14

    Abstract: An oscillator including a switched capacitor configured to generate a sawtooth or ramp voltage in response to a switched capacitor drive signal; a low pass filter (LPF) configured to filter the sawtooth or ramp voltage to generate a filtered voltage; a reference voltage generator configured to generate a reference voltage; an integrator configured to integrate a difference between the sawtooth or ramp voltage and the reference voltage to generate a frequency control signal; a voltage controlled oscillator (VCO) configured to generate a first clock based on the frequency control signal; a frequency divider configured to frequency divide the first clock to generate a second clock; and a switched capacitor driver configured to generate the switched capacitor drive signal in response to the second clock. The oscillator may also include a switched capacitor sampler to sample the sawtooth or ramp voltage, wherein the filtered voltage is based on the sampled voltage.

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