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公开(公告)号:US20180231609A1
公开(公告)日:2018-08-16
申请号:US15835227
申请日:2017-12-07
Applicant: QUALCOMM Incorporated
Inventor: Arvind JAIN , Nishi BHUSHAN SINGH , Rahul GULATI , Pranjal BHUYAN , Rakesh Kumar KINGER , Roberto AVERBUJ
IPC: G01R31/317 , G01R31/3187 , G01R31/3183 , G01R31/3185 , G01R31/319
Abstract: A self-test controller includes a memory configured to store a test patterns, configuration registers, and a memory data component. The test patterns are encoded in the memory using various techniques in order to save storage space. By using the configuration parameters, the memory data component is configured to decode the test patterns and perform multiple built-in self-test on a multitude of test cores. The described techniques allow for built-in self-test to be performed dynamically while utilizing less space in the memory.
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公开(公告)号:US20190088348A1
公开(公告)日:2019-03-21
申请号:US15887695
申请日:2018-02-02
Applicant: QUALCOMM Incorporated
Inventor: Arvind JAIN , Nishi BHUSHAN SINGH , Roberto AVERBUJ , Daniel LEWIS
Abstract: Disclosed are methods and apparatus for implementing a memory controller, such as a bus integrated memory controller (BIMC) that includes a memory built-in-self-test (MBIST) controller or logic. The MBIST controller is configured for testing at least one memory device, such as stacked low power double data rate (LPDDR) memories in a system on a chip or similar constructions that make external testing of the memory device difficult. The MBIST controller may be implemented within a standard memory controller and includes a memory translation logic configured to translate signals for testing the at least one memory device into signals in a format that is usable by the at least one memory device, where the translation logic serves to effectuate a memory representation.
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