MEMORY TEST CONTROL FOR STACKED DDR MEMORY
    2.
    发明申请

    公开(公告)号:US20190088348A1

    公开(公告)日:2019-03-21

    申请号:US15887695

    申请日:2018-02-02

    Abstract: Disclosed are methods and apparatus for implementing a memory controller, such as a bus integrated memory controller (BIMC) that includes a memory built-in-self-test (MBIST) controller or logic. The MBIST controller is configured for testing at least one memory device, such as stacked low power double data rate (LPDDR) memories in a system on a chip or similar constructions that make external testing of the memory device difficult. The MBIST controller may be implemented within a standard memory controller and includes a memory translation logic configured to translate signals for testing the at least one memory device into signals in a format that is usable by the at least one memory device, where the translation logic serves to effectuate a memory representation.

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