公开(公告)号：US20190088348A1

公开(公告)日：2019-03-21

申请号：US15887695

申请日：2018-02-02

Applicant: QUALCOMM Incorporated

Inventor： Arvind JAIN ,  Nishi BHUSHAN SINGH ,  Roberto AVERBUJ ,  Daniel LEWIS

IPC: G11C29/36 ,  G11C29/12 ,  G11C29/14

Abstract: Disclosed are methods and apparatus for implementing a memory controller, such as a bus integrated memory controller (BIMC) that includes a memory built-in-self-test (MBIST) controller or logic. The MBIST controller is configured for testing at least one memory device, such as stacked low power double data rate (LPDDR) memories in a system on a chip or similar constructions that make external testing of the memory device difficult. The MBIST controller may be implemented within a standard memory controller and includes a memory translation logic configured to translate signals for testing the at least one memory device into signals in a format that is usable by the at least one memory device, where the translation logic serves to effectuate a memory representation.

公开(公告)号：US20240087662A1

公开(公告)日：2024-03-14

申请号：US17944691

申请日：2022-09-14

Applicant: QUALCOMM INCORPORATED

Inventor： HONG DAI ,  Amir BOROVIETZKY ,  Arvind JAIN ,  Massine BITAM ,  Madan KRISHNAPPA

IPC: G11C29/32 ,  G01R31/319 ,  G11C29/44

CPC classification number: G11C29/32 ,  G01R31/31926 ,  G11C29/44

Abstract: A system for repairing a random access memory may include serial test interface logic, fuse-sense logic, a repair data register chain, and multiplexing logic. The repair data register chain may include serially interconnected data registers configured to shift data through the repair data register chain. Each data register of the repair data register chain may have a data output configured to be coupled to a repair information input of the random access memory. The multiplexing logic may be configured to provide a soft-repair mode and a hard-repair mode. When the soft-repair mode is selected, the multiplexing logic may be configured to receive soft-repair data provided by the serial test interface logic into the data registers. When the hard-repair mode is selected, the multiplexing logic may be configured to receive the data provided by the fuse-sense logic into the data registers.

公开(公告)号：US20230315141A1

公开(公告)日：2023-10-05

申请号：US17707621

申请日：2022-03-29

Applicant: QUALCOMM Incorporated

Inventor： Arvind JAIN ,  Divya GANGADHARAN ,  Muhammad NASIR ,  Hong DAI ,  Madan KRISHNAPPA

IPC: G06F1/06 ,  H04B1/401 ,  G01R31/317

CPC classification number: G06F1/06 ,  H04B1/401 ,  G01R31/31727

Abstract: An aspect of the disclosure relates to an integrated circuit (IC). The IC includes a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively; and a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively.

公开(公告)号：US20180231609A1

公开(公告)日：2018-08-16

申请号：US15835227

申请日：2017-12-07

Applicant: QUALCOMM Incorporated

Inventor： Arvind JAIN ,  Nishi BHUSHAN SINGH ,  Rahul GULATI ,  Pranjal BHUYAN ,  Rakesh Kumar KINGER ,  Roberto AVERBUJ

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/319

Abstract: A self-test controller includes a memory configured to store a test patterns, configuration registers, and a memory data component. The test patterns are encoded in the memory using various techniques in order to save storage space. By using the configuration parameters, the memory data component is configured to decode the test patterns and perform multiple built-in self-test on a multitude of test cores. The described techniques allow for built-in self-test to be performed dynamically while utilizing less space in the memory.