公开(公告)号：US20240411718A1

公开(公告)日：2024-12-12

申请号：US18333377

申请日：2023-06-12

Applicant: QUALCOMM Incorporated

Inventor： Sandeep PANDE ,  Satish SINGH ,  Colin Beaton VERRILLI ,  Natarajan VAIDHYANATHAN ,  Vinay MURTHY

IPC: G06F15/80 ,  G06F9/50

Abstract: A machine learning (ML)-accelerator system-on-chip (SoC) is described. The ML-accelerator SoC includes a set of ML-accelerator cores. The ML-accelerator SoC also includes a network-on-chip (NoC) coupled to the set of ML-accelerator cores. The ML-accelerator SoC further includes an inference video post processing (infVPP) module coupled to the NoC. The ML-accelerator SoC also includes a video decoder coupled to the NoC.

公开(公告)号：US20240095872A1

公开(公告)日：2024-03-21

申请号：US17946753

申请日：2022-09-16

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton VERRILLI ,  Natarajan VAIDHYANATHAN ,  Matthew SIMPSON ,  Geoffrey Carlton BERRY ,  Sandeep PANDE

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0673

Abstract: A processor-implemented method for a memory storage format to accelerate machine learning (ML) on a computing device is described. The method includes receiving an image in a first layer storage format of a neural network. The method also includes assigning addresses to image pixels of each of three channels of the first layer storage format for accessing the image pixels in a blocked ML storage acceleration format. The method further includes storing the image pixels in the blocked ML storage acceleration format according to the assigned addresses of the image pixels. The method also includes accelerating inference video processing of the image according to the assigned addresses for the image pixels corresponding to the blocked ML storage acceleration format.