公开(公告)号：US20200004550A1

公开(公告)日：2020-01-02

申请号：US16024725

申请日：2018-06-29

Applicant: QUALCOMM Incorporated

Inventor： Harsh THAKKER ,  Thomas Philip SPEIER ,  Rodney Wayne SMITH ,  Kevin JAGET ,  James Norris DIEFFENDERFER ,  Michael MORROW ,  Pritha GHOSHAL ,  Yusuf Cagatay TEKMEN ,  Brian STEMPEL ,  Sang Hoon LEE ,  Manish GARG

IPC: G06F9/38 ,  G06F9/30

Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.