公开(公告)号：US20160092221A1

公开(公告)日：2016-03-31

申请号：US14498938

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Brian Michael STEMPEL ,  James Norris DIEFFENDERFER ,  Michael Scott MCILVAINE ,  Melinda BROWN

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30072 ,  G06F9/30149 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3885

Abstract: Systems and methods for dependency-prediction include executing instructions in an instruction pipeline of a processor and detecting a conditionality-imposing control instruction, such as an If-Then (IT) instruction, which imposes dependent behavior on a conditionality block size of one or more dependent instructions. Prior to executing a first instruction, a dependency-prediction is made to determine if the first instruction is a dependent instruction of the conditionality-imposing control instruction, based on the conditionality block size and one or more parameters of the instruction pipeline. The first instruction is executed based on the dependency-prediction. When the first instruction is dependency-mispredicted, an associated dependency-misprediction penalty is mitigated. If the first instruction is a branch instruction, the mitigation involves training a branch prediction tracking mechanism to correctly dependency-predict future occurrences of the first instruction.

Abstract translation: 用于依赖性预测的系统和方法包括在处理器的指令流水线中执行指令，并且检测诸如If-Then（IT）指令之类的有条件的控制指令，该指令将依赖行为强加于一个或多个 依赖说明。 在执行第一指令之前，基于条件块大小和指令流水线的一个或多个参数，进行依赖性预测以确定第一指令是否是条件施加控制指令的依赖指令。 基于依赖关系预测执行第一指令。 当第一条指令是依赖性错误预测时，减轻相关的依赖关系错误估计。 如果第一指令是分支指令，则缓解涉及训练分支预测跟踪机制以正确依赖 - 预测第一指令的将来出现。

公开(公告)号：US20180173631A1

公开(公告)日：2018-06-21

申请号：US15594631

申请日：2017-05-14

Applicant: QUALCOMM Incorporated

Inventor： Thomas Andrew SARTORIUS ,  James Norris DIEFFENDERFER ,  Thomas Philip SPEIER ,  Michael Scott MCILVAINE ,  Michael William MORROW

IPC: G06F12/0862 ,  G06F17/30

CPC classification number: G06F12/0862 ,  G06F16/24558 ,  G06F2212/6024 ,  G06F2212/6026

Abstract: Systems and methods are directed to prefetch mechanisms involving non-equal magnitude stride values. A non-equal magnitude functional relationship between successive stride values, may be detected, wherein the stride values are based on distances between target addresses of successive load instructions. At least a next stride value for prefetching data, may be determined, wherein the next stride value is based on the non-equal magnitude functional relationship and a previous stride value. Data prefetch may be from at least one prefetch address calculated based on the next stride value and a previous target address. The non-equal magnitude functional relationship may include a logarithmic relationship corresponding to a binary search algorithm.

公开(公告)号：US20170046158A1

公开(公告)日：2017-02-16

申请号：US14827245

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Luke YEN ,  Michael William MORROW ,  Thomas Philip SPEIER ,  James Norris DIEFFENDERFER

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/383

Abstract: Systems and methods for identifying candidate load instructions for prefetch operations based on at least instruction encoding of the load instructions, include an identifier based on a function of at least one or more fields of a load instruction and optionally, a subset of bits of the PC value of the load instruction, wherein the one or more fields exclude a full address or program counter (PC) value of the load instruction. Prefetch mechanisms, including a prefetch table indexed by the identifier, can determine whether the load instruction is a candidate load instruction for prefetching load data, based on the identifier. The function may be a hash, a concatenation, or a combination thereof, of one or more bits of the one or more fields. The fields include one or more of a base register, a destination register, an immediate offset, an offset register, or other bits of instruction encoding of the load instruction.

Abstract translation: 用于基于至少指令编码加载指令来识别用于预取操作的候选加载指令的系统和方法包括基于加载指令的至少一个或多个字段的功能的标识符，以及可选地，PC的位的子集 值，其中一个或多个字段排除加载指令的完整地址或程序计数器（PC）值。 预取机制，包括由标识符索引的预取表，可以基于标识符来确定加载指令是否是用于预取负载数据的候选加载指令。 该功能可以是一个或多个字段的一个或多个比特的散列，连接或其组合。 这些字段包括基本寄存器，目的地寄存器，立即偏移量，偏移寄存器或加载指令的指令编码的其他位中的一个或多个。

公开(公告)号：US20200004550A1

公开(公告)日：2020-01-02

申请号：US16024725

申请日：2018-06-29

Applicant: QUALCOMM Incorporated

Inventor： Harsh THAKKER ,  Thomas Philip SPEIER ,  Rodney Wayne SMITH ,  Kevin JAGET ,  James Norris DIEFFENDERFER ,  Michael MORROW ,  Pritha GHOSHAL ,  Yusuf Cagatay TEKMEN ,  Brian STEMPEL ,  Sang Hoon LEE ,  Manish GARG

IPC: G06F9/38 ,  G06F9/30

Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

公开(公告)号：US20170249144A1

公开(公告)日：2017-08-31

申请号：US15055160

申请日：2016-02-26

Applicant: QUALCOMM Incorporated

Inventor： Kevin JAGET ,  Michael William MORROW ,  James Norris DIEFFENDERFER

IPC: G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30021 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3455 ,  G06F9/3824 ,  G06F9/3832

Abstract: Aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in processors. An exemplary method includes detecting a pattern of pipelined instructions to access memory using a first portion of available bus width and, in response to detecting the pattern, combining the pipelined instructions into a single instruction to access the memory using a second portion of the available bus width that is wider than the first portion. Devices including processors using disclosed aspects may execute currently available software in a more efficient manner without the software being modified.

公开(公告)号：US20170255569A1

公开(公告)日：2017-09-07

申请号：US15057121

申请日：2016-03-01

Applicant: QUALCOMM Incorporated

Inventor： Thomas Andrew SARTORIUS ,  James Norris DIEFFENDERFER ,  Michael William MORROW ,  Jeffrey Todd BRIDGES ,  Michael Scott MCILVAINE ,  Rodney Wayne SMITH ,  Kenneth Alan DOCKSER ,  Thomas Philip SPEIER

IPC: G06F12/12 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/123 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/126 ,  G06F2212/604 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/684

Abstract: Systems and methods for managing access to a cache relate to determining one or more execute permissions associated with a write-address of a write-request to the cache. The cache may be a unified cache for storing data as well as instructions. If there is a write-miss in the cache for the write-request, a cache controller may determine whether to implement a write-allocate policy or a write-no-allocate policy for servicing the write-miss, based on the one or more execute permissions. The one or more execute permissions can relate to a privilege level associated with the write-address. Execute permissions of a producing agent which generated the write-request and an execute permission of a consuming agent which can execute from the write-address may be based on the privilege levels of the producing agent and the consuming agent, respectively.

公开(公告)号：US20170083333A1

公开(公告)日：2017-03-23

申请号：US14859356

申请日：2015-09-21

Applicant: QUALCOMM Incorporated

Inventor： Niket Kumar CHOUDHARY ,  Michael Scott MCILVAINE ,  Daren Eugene STREETT ,  Vimal Kodandarama REDDY ,  Shekhar Shashi SRIKANTAIAH ,  Sandeep Suresh NAVADA ,  Robert Douglas CLANCY ,  James Norris DIEFFENDERFER ,  Thomas Andrew SARTORIUS

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30058 ,  G06F9/3808 ,  G06F12/0875 ,  G06F2212/452

Abstract: Systems and methods pertain to a branch target instruction cache (BTIC) of a processor. The BTIC is configured to store one or more branch target instructions at branch target addresses of branch instructions executable by the processor. At least one of the branch target instructions stored in the BTIC is a conditional branch instruction. Branch prediction techniques for predicting the direction of the conditional branch instruction allow one or more instructions following the conditional branch instruction, as well as a branch target address of the conditional branch instruction to also be stored in the BTIC.

公开(公告)号：US20160350116A1

公开(公告)日：2016-12-01

申请号：US14726450

申请日：2015-05-29

Applicant: QUALCOMM Incorporated

Inventor： Vimal Kodandarama REDDY ,  Niket Kumar CHOUNDHARY ,  Michael Scott MCILVAINE ,  Daren Eugene STREETT ,  Robert Douglas CLANCY ,  James Norris DIEFFENDERFER ,  Michael William MORROW

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/3844

Abstract: Systems and methods for mitigating influence of wrong-path branch instructions in branch prediction include a branch prediction write queue. A first entry of the branch prediction write queue is associated with a first branch instruction based on an order in which the first branch instruction is fetched. Upon speculatively executing the first branch instruction, a correct direction of the first branch instruction is written in the first entry. Prior to committing the first branch instruction, the branch prediction write queue is configured to update one or more branch prediction mechanisms based on the first entry if the first branch instruction was speculatively executed in a correct-path. Updates to the one or more branch prediction mechanisms based on the first entry are prevented if the first branch instruction was speculatively executed in a wrong-path.

Abstract translation: 用于减轻分支预测中错误路径分支指令的影响的系统和方法包括分支预测写入队列。 分支预测写入队列的第一条目基于获取第一分支指令的顺序与第一分支指令相关联。 在推测性地执行第一分支指令时，在第一条目中写入第一分支指令的正确方向。 在提交第一分支指令之前，如果在正确路径中推测性地执行第一分支指令，则分支预测写入队列被配置为基于第一条目来更新一个或多个分支预测机制。 如果在错误路径中推测性地执行第一分支指令，则可以防止基于第一条目对一个或多个分支预测机制的更新。

公开(公告)号：US20160342530A1

公开(公告)日：2016-11-24

申请号：US14716947

申请日：2015-05-20

Applicant: QUALCOMM Incorporated

Inventor： Henry Arthur PELLERIN, III ,  Thomas Philip SPEIER ,  Thomas Andrew SARTORIUS ,  Michael William MORROW ,  James Norris DIEFFENDERFER ,  Kenneth Alan DOCKSER ,  Michael Scott MCILVAINE

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/401 ,  G06F2212/6032 ,  G06F2212/621

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract translation: 存储器结构使用索引标签压缩结构压缩存储器标签的一部分。 存储器标签的一组较高位可以存储在索引标签压缩结构中，其中较高位的集合由索引值标识。 标签阵列存储存储器标签的一组较低位，以及标识在存储标签的较高位的集合的标签压缩结构中的条目的索引值。 存储器标签可以包括存储在数据阵列中的数据元素的存储器地址的至少一部分。