公开(公告)号：US20250079281A1

公开(公告)日：2025-03-06

申请号：US18458242

申请日：2023-08-30

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Joan Rey Villarba Buot ,  Sang-Jae Lee ,  Zhijie Wang ,  Michelle Yejin Kim

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: Hybrid package substrates employing film metallization layers with outer pre-impregnated (PPG) region(s) to support high density bump and wire bond connections for respective bump and wire bond connected dies in the IC package, and related hybrid integrated circuit (IC) packages and fabrication methods are disclosed. The package substrate includes film metallization layers of a softer, flexible material that can more easily be patterned to support formation of high density, reduced pitch metal interconnects to support finer bump pitch connections to a bottom, first die(s) in a die region of the package substrate. The package substrate also includes one or more PPG regions a PPG metallization layer(s) adjacent to the die region of the package substrate that reinforces the film metallization layers and also supports the formation of wire bond pads for wire bond connections to an upper, second die(s) in the hybrid IC package.

公开(公告)号：US20250062235A1

公开(公告)日：2025-02-20

申请号：US18450636

申请日：2023-08-16

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Hong Bok We ,  Zhijie Wang ,  Sang-Jae Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/16

Abstract: Package substrate with metallization layer(s) that includes an additional metal pad layer to facilitate reduced via size for reduced bump pitch, and related integrated circuit (IC) packages and fabrication methods. An additional metal pad(s) is provided in an insulating layer of a metallization layer(s) of the package substrate in which a via(s) is formed to reduce vertical connectivity distance between metal interconnects in adjacent metallization layers electrically coupled together by the via. This can reduce the aspect ratio and size of the via thereby allowing metal interconnects that are electrically coupled to the via to also be reduced in size (e.g., width) while still supporting an aligned, low resistance connection between the via(s) and the metal interconnects. Being able to reduce the size (e.g., width) of the metal interconnects can reduce bump pitch of the package substrate, which can facilitate a higher density of die/bump connections to the package substrate.

公开(公告)号：US20240332146A1

公开(公告)日：2024-10-03

申请号：US18193295

申请日：2023-03-30

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Hong Bok We ,  Zhijie Wang ,  Sang-Jae Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/42 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L24/83 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/83

Abstract: Integrated circuit (IC) package employing metal posts thermally coupling a die to an interposer substrate for dissipating thermal energy of the die are disclosed. In one aspect, the IC package includes a metal post(s) thermally coupled to the die. The metal post(s) is attached to metal interconnect(s) (e.g., metal trace, metal pad, metal line, metal plate) in the interposer substrate. In this manner, as thermal energy is generated in the die, this thermal energy dissipates through the metal post(s) and through the coupled metal interconnect(s) into the interposer substrate. Thus, metal interconnects, which are an available feature in an interposer substrate fabrication process, are deployed to form the foundation upon which metal posts are fabricated and thermally coupled to the die to provide heat dissipation for the die in the IC package.