公开(公告)号：US20240038753A1

公开(公告)日：2024-02-01

申请号：US17816502

申请日：2022-08-01

申请人： QUALCOMM Incorporated

发明人： Aniket Patil ,  Hong Bok We ,  Joan Rey Villarba Buot

IPC分类号： H01L27/01 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L27/01 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/03 ,  H01L23/5383 ,  H01L25/0652 ,  H01L24/04 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/05073 ,  H01L2224/0231 ,  H01L2224/039 ,  H01L2224/05573 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/06138 ,  H01L24/16 ,  H01L2224/16225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L24/92 ,  H01L2224/92125

摘要： Deep trench capacitors (DTCs) employing bypass metal trace signal routing supporting signal bypass routing, and related integrated circuit (IC) packages and fabrication methods are disclosed. The DTC includes an outer metallization layer (e.g., a redistribution layer (RDL)) to provide an external interface to the DTC. In exemplary aspects, to make available signal routes that can extend through a DTC, an outer metallization layer of the DTC includes additional metal interconnects. These additional metal interconnects are not coupled the capacitors in the DTC. These additional metal interconnects are interconnected to each other by metal traces (e.g., metal lines) in the outer metallization layer of the DTC to provide bypass signal routes through the DTC. This is opposed to signal paths in a package substrate in which the DTC is coupled or embedded having to be routed around the DTC in the package substrate.

公开(公告)号：US20240250009A1

公开(公告)日：2024-07-25

申请号：US18158225

申请日：2023-01-23

申请人： QUALCOMM Incorporated

发明人： Seongryul Choi ,  Joan Rey Villarba Buot ,  Kuiwon Kang ,  Zhijie Wang

IPC分类号： H01L23/498 ,  H01L21/288 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L21/288 ,  H01L21/76829 ,  H01L23/49816 ,  H01L24/04 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/08112 ,  H01L2224/08225 ,  H01L2224/16014 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/48105 ,  H01L2224/48225

摘要： Embedded trace substrates (ETS) having an ETS metallization layer with T-shaped interconnects with reduced-width embedded metal traces, and related integrated circuit (IC) packages and fabrication methods. The ETS includes an outer ETS metallization layer that includes T-shaped interconnects for supporting input/output (I/O) connections between the ETS and another opposing package substrate. To increase density of I/O interconnections, the pitch of the embedded metal traces in the ETS metallization layer is reduced. The T-shaped interconnects also each include an additional metal contact pad that is coupled to a respective embedded metal trace to increase the height of the embedded metal trace to eliminate a vertical connection gap between the ETS and an opposing package substrate. In the T-shape interconnects, their embedded metal traces are reduced in width in a horizontal direction(s) as compared to their respective metal contact pads to provide room for additional metal traces for additional signal routing capacity.

公开(公告)号：US11764076B2

公开(公告)日：2023-09-19

申请号：US17107512

申请日：2020-11-30

申请人： QUALCOMM Incorporated

发明人： Kuiwon Kang ,  Joan Rey Villarba Buot ,  Terence Cheung

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L21/4857 ,  H01L21/481 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238

摘要： Certain aspects of the present disclosure generally relate to an embedded trace substrate with partially buried traces, methods for fabrication thereof, and apparatus comprising such an embedded trace substrate. One example method of fabricating an embedded trace substrate generally includes creating a pattern of conductive traces above a dielectric layer and mechanically pressing on the pattern of conductive traces such that lower portions of the conductive traces are buried in the dielectric layer.

公开(公告)号：US20230114404A1

公开(公告)日：2023-04-13

申请号：US17822589

申请日：2022-08-26

申请人： QUALCOMM Incorporated

发明人： Seongryul Choi ,  Kuiwon Kang ,  Joan Rey Villarba Buot

IPC分类号： H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

摘要： Embedded trace substrate (ETS) with embedded metal traces having multiple thicknesses for integrated circuit (IC) package height control, and related IC packages and fabrication methods. The IC package includes a die that is coupled to a package substrate to provide signal routing paths to the die. The IC package also includes an ETS that includes metal traces embedded in an insulating layer(s) to provide connections for signal routing paths for the IC package. To control (such as to reduce) the height of the IC package, the embedded metal traces embedded in an insulating layer in the ETS are provided to have multiple thicknesses (i.e., heights) in a vertical direction. The embedded metal traces in the ETS whose thicknesses affect the overall height of the IC package by being coupled to interconnects external to the ETS in the vertical direction, can be reduced in thickness to control IC package height.

公开(公告)号：US11562962B2

公开(公告)日：2023-01-24

申请号：US17148367

申请日：2021-01-13

申请人： QUALCOMM Incorporated

发明人： Joan Rey Villarba Buot ,  Aniket Patil ,  Zhijie Wang ,  Hong Bok We

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

摘要： A package comprising a substrate comprising a plurality of interconnects, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, and an interconnect device coupled to the substrate. The first integrated device, the second integrated device, the interconnect device and the substrate are configured to provide an electrical path for an electrical signal between the first integrated device and the second integrated device, that extends through at least the substrate, through the interconnect device and back through the substrate. The electrical path includes at least one interconnect that extends diagonally.

公开(公告)号：US12100645B2

公开(公告)日：2024-09-24

申请号：US17482718

申请日：2021-09-23

申请人： QUALCOMM Incorporated

发明人： Aniket Patil ,  Hong Bok We ,  Joan Rey Villarba Buot

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L23/49838 ,  H01L21/4846 ,  H01L23/49822

摘要： Integrated circuit (IC) packages employing added metal for embedded metal traces in an ETS-based substrate for reduced signal path impedance. An IC package includes a package substrate and an ETS metallization layer disposed on the package substrate. To mitigate or offset an increase in impedance in longer signal paths between die circuitry and the package substrate that can result in decreased signaling speed and/or increased signal loss, added metal interconnects are coupled to embedded metal traces in the ETS metallization layer. Thus, embedded metal traces of the ETS metallization layer coupled to signal/ground signal paths of the die are increased in metal surface area. Increasing metal surface area of embedded metal traces coupled to the signal/ground signal paths of a die increases capacitance of such signal/ground signal paths. Increasing capacitance of signal/ground signal paths decreases impedance of the signal/ground signal paths to mitigate or reduce signaling delay and/or loss.

公开(公告)号：US11955409B2

公开(公告)日：2024-04-09

申请号：US17148257

申请日：2021-01-13

申请人： QUALCOMM Incorporated

发明人： Aniket Patil ,  Joan Rey Villarba Buot ,  Hong Bok We

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/12 ,  H01L23/66

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/12 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6638

摘要： A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

公开(公告)号：US11791276B2

公开(公告)日：2023-10-17

申请号：US17225949

申请日：2021-04-08

申请人： QUALCOMM Incorporated

发明人： Aniket Patil ,  Hong Bok We ,  Joan Rey Villarba Buot

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/19103 ,  H01L2924/19105

摘要： A device comprising a first substrate comprising a first plurality of pillar interconnects; a second substrate comprising a second plurality of pillar interconnects, wherein the second plurality of pillar interconnects is coupled to the first plurality of pillar interconnects through a plurality of solder interconnects; a passive component located between the first substrate and the second substrate; and an integrated device coupled to the first substrate.

公开(公告)号：US20230083146A1

公开(公告)日：2023-03-16

申请号：US17474524

申请日：2021-09-14

申请人： QUALCOMM Incorporated

发明人： Hong Bok We ,  Joan Rey Villarba Buot ,  Aniket Patil

IPC分类号： H01Q1/22 ,  H01Q1/52 ,  H01Q1/42 ,  H01Q9/04 ,  H01Q21/06 ,  H01Q1/38

摘要： Multi-sided antenna modules employing antennas on multiple sides of a package substrate for enhanced antenna coverage, and related antenna module fabrication methods. The multi-sided antenna module includes an integrated circuit (IC) die(s) disposed on a first side of the package substrate. The multi-sided antenna module further includes first and second substrate antenna layers disposed on respective first and second sides of the package substrate. The first substrate antenna layer includes a first antenna(s) disposed on the first side of the package substrate adjacent to the IC die(s). The second substrate antenna layer includes a second antenna(s) disposed on the second side of the package substrate opposite of the first side of the package substrate. In this manner, the multi-sided antenna module, including antennas on multiple sides of the package substrate, provides antenna coverage that extends from both sides of the package substrate to provide multiple directions of coverage.

公开(公告)号：US11302656B2

公开(公告)日：2022-04-12

申请号：US16938316

申请日：2020-07-24

申请人： QUALCOMM Incorporated

发明人： Hong Bok We ,  Aniket Patil ,  Joan Rey Villarba Buot ,  Zhijie Wang

IPC分类号： H01L23/64 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

摘要： An integrated circuit (IC) package is described. The IC package includes a package substrate, composed of a substrate core, a first power rail on a first surface of the substrate core, and a second power rail on a second surface of the substrate core. The IC package includes a logic die supported by the second power rail on the second surface of the substrate core. The IC package includes passive devices within the substrate core. Each of the passive devices has a first terminal and a second terminal opposite the first terminal. The first terminal of each of the passive devices is directly coupled to the first power rail, and the second terminal of each of the plurality of the passive devices is directly coupled to the second power rail. The IC package includes package bumps on the second power rail on the second surface of the substrate core.