公开(公告)号：US20190086982A1

公开(公告)日：2019-03-21

申请号：US16129417

申请日：2018-09-12

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  SeyedMajid Zahedi ,  Derek Robert Hower ,  Carl Alan Waldspurger ,  Jeffrey Todd Bridges ,  Sanjay Bhikhubhai Patel ,  Gabriel Martel Tarr ,  Chih Kang Lin ,  Ryan Donovan Wells ,  Harold Wade Cain, III

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3206 ,  G06F1/3296

Abstract: Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements is disclosed. Current from a power rail is allocated to CPUs by a global current manger (GCM) circuit related to performance criteria set by CPUs. The CPUs can request increased current allocation from the GCM circuit, such as in response to executing a higher performance task. If the increased current allocation request keeps total current on the power rail within its maximum rail current limit, the GCM circuit approves the request to allow the CPU increased current allocation. This can allow CPUs executing higher performance tasks to have a larger current allocation than CPUs executing lower performance tasks without the maximum rail current limit being exceeded, and without having to necessarily lower voltage of the power rail, which could unnecessarily lower performance of all CPUs.

公开(公告)号：US10831254B2

公开(公告)日：2020-11-10

申请号：US16129417

申请日：2018-09-12

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  SeyedMajid Zahedi ,  Derek Robert Hower ,  Carl Alan Waldspurger ,  Jeffrey Todd Bridges ,  Sanjay Bhikhubhai Patel ,  Gabriel Martel Tarr ,  Chih Kang Lin ,  Ryan Donovan Wells ,  Harold Wade Cain, III

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3296

Abstract: Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements is disclosed. Current from a power rail is allocated to CPUs by a global current manger (GCM) circuit related to performance criteria set by CPUs. The CPUs can request increased current allocation from the GCM circuit, such as in response to executing a higher performance task. If the increased current allocation request keeps total current on the power rail within its maximum rail current limit, the GCM circuit approves the request to allow the CPU increased current allocation. This can allow CPUs executing higher performance tasks to have a larger current allocation than CPUs executing lower performance tasks without the maximum rail current limit being exceeded, and without having to necessarily lower voltage of the power rail, which could unnecessarily lower performance of all CPUs.