公开(公告)号：US10678690B2

公开(公告)日：2020-06-09

申请号：US15689543

申请日：2017-08-29

Applicant: QUALCOMM Incorporated

Inventor： Derek Robert Hower ,  Carl Alan Waldspurger ,  Vikramjit Sethi

IPC: G06F12/0846 ,  G06F12/02 ,  G06F13/16 ,  G06F9/50 ,  G06F12/0842

Abstract: Providing fine-grained Quality of Service (QoS) control using interpolation for partitioned resources in processor-based systems is disclosed. In this regard, in one aspect, a processor-based system provides a partitioned resource (such as a system cache or memory access bandwidth to a shared system memory) that is subdivided into a plurality of partitions, and that is configured to service a plurality of resource clients. A resource allocation agent of the processor-based system provides a plurality of allocation indicators corresponding to each combination of resource client and partition, and indicating an allocation of each partition for each resource client. The resource allocation agent allocates the partitioned resource among the resource clients based on an interpolation of the plurality of allocation indicators. Because each allocation indicator may be different for each combination of resource client and partition, interpolation of the allocation indicators provides a higher-resolution aggregate resource allocation for each resource client.

公开(公告)号：US10831254B2

公开(公告)日：2020-11-10

申请号：US16129417

申请日：2018-09-12

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  SeyedMajid Zahedi ,  Derek Robert Hower ,  Carl Alan Waldspurger ,  Jeffrey Todd Bridges ,  Sanjay Bhikhubhai Patel ,  Gabriel Martel Tarr ,  Chih Kang Lin ,  Ryan Donovan Wells ,  Harold Wade Cain, III

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3296

Abstract: Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements is disclosed. Current from a power rail is allocated to CPUs by a global current manger (GCM) circuit related to performance criteria set by CPUs. The CPUs can request increased current allocation from the GCM circuit, such as in response to executing a higher performance task. If the increased current allocation request keeps total current on the power rail within its maximum rail current limit, the GCM circuit approves the request to allow the CPU increased current allocation. This can allow CPUs executing higher performance tasks to have a larger current allocation than CPUs executing lower performance tasks without the maximum rail current limit being exceeded, and without having to necessarily lower voltage of the power rail, which could unnecessarily lower performance of all CPUs.

公开(公告)号：US20190086982A1

公开(公告)日：2019-03-21

申请号：US16129417

申请日：2018-09-12

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  SeyedMajid Zahedi ,  Derek Robert Hower ,  Carl Alan Waldspurger ,  Jeffrey Todd Bridges ,  Sanjay Bhikhubhai Patel ,  Gabriel Martel Tarr ,  Chih Kang Lin ,  Ryan Donovan Wells ,  Harold Wade Cain, III

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3206 ,  G06F1/3296

Abstract: Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements is disclosed. Current from a power rail is allocated to CPUs by a global current manger (GCM) circuit related to performance criteria set by CPUs. The CPUs can request increased current allocation from the GCM circuit, such as in response to executing a higher performance task. If the increased current allocation request keeps total current on the power rail within its maximum rail current limit, the GCM circuit approves the request to allow the CPU increased current allocation. This can allow CPUs executing higher performance tasks to have a larger current allocation than CPUs executing lower performance tasks without the maximum rail current limit being exceeded, and without having to necessarily lower voltage of the power rail, which could unnecessarily lower performance of all CPUs.

公开(公告)号：US20180081579A1

公开(公告)日：2018-03-22

申请号：US15272951

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Carl Alan Waldspurger ,  Natarajan Vaidhyanathan ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Koustav Bhattacharya

IPC: G06F3/06 ,  G06F12/0891

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0685 ,  G06F12/0802 ,  G06F12/0891 ,  G06F13/1668 ,  G06F13/1694 ,  G06F2212/20 ,  G06F2212/60

Abstract: Providing flexible management of heterogeneous memory systems using spatial Quality of Service (QoS) tagging in processor-based systems is disclosed. In one aspect, a heterogeneous memory system of a processor-based system includes a first memory and a second memory. The heterogeneous memory system is divided into a plurality of memory regions, each associated with a QoS identifier (QoSID), which may be set and updated by software. A memory controller of the heterogeneous memory system provides a QoS policy table, which operates to associate each QoSID with a QoS policy state, and which also may be software-configurable. Upon receiving a memory access request including a memory address of a memory region, the memory controller identifies a software-configurable QoSID associated with the memory address, and associates the QoSID with a QoS policy state using the QoS policy table. The memory controller then applies the QoS policy state to perform the memory access operation.

公开(公告)号：US11221971B2

公开(公告)日：2022-01-11

申请号：US15274665

申请日：2016-09-23

Applicant: QUALCOMM Incorporated

Inventor： Derek Hower ,  Harold Wade Cain, III ,  Carl Alan Waldspurger

IPC: G06F13/16 ,  G06F12/0811 ,  G06F9/54

Abstract: Systems and methods are directed to managing access to a shared memory. A request received at a memory controller, for access to the shared memory from a client of one or more clients configured to access the shared memory, is placed in at least one queue in the memory controller. A series of one or more timeout values is assigned to the request, based, at least in part on a priority associated with the client which generated the request. The priority may be fixed or based on a Quality-of-Service (QoS) class of the client. A timer is incremented while the request remains in the first queue. As the timer traverses each one of the one or more timeout values in the series, a criticality level of the request is incremented. A request with a higher criticality level may be prioritized for servicing over a request with a lower criticality level.

公开(公告)号：US20190065374A1

公开(公告)日：2019-02-28

申请号：US15689543

申请日：2017-08-29

Applicant: QUALCOMM Incorporated

Inventor： Derek Robert Hower ,  Carl Alan Waldspurger ,  Vikramjit Sethi

IPC: G06F12/0846 ,  G06F12/02 ,  G06F13/16

Abstract: Providing fine-grained Quality of Service (QoS) control using interpolation for partitioned resources in processor-based systems is disclosed. In this regard, in one aspect, a processor-based system provides a partitioned resource (such as a system cache or memory access bandwidth to a shared system memory) that is subdivided into a plurality of partitions, and that is configured to service a plurality of resource clients. A resource allocation agent of the processor-based system provides a plurality of allocation indicators corresponding to each combination of resource client and partition, and indicating an allocation of each partition for each resource client. The resource allocation agent allocates the partitioned resource among the resource clients based on an interpolation of the plurality of allocation indicators. Because each allocation indicator may be different for each combination of resource client and partition, interpolation of the allocation indicators provides a higher-resolution aggregate resource allocation for each resource client.

公开(公告)号：US10055158B2

公开(公告)日：2018-08-21

申请号：US15272951

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Carl Alan Waldspurger ,  Natarajan Vaidhyanathan ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Koustav Bhattacharya

IPC: G06F12/0891 ,  G06F3/06 ,  G06F12/0802 ,  G06F13/16

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0685 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/126 ,  G06F13/1668 ,  G06F13/1694 ,  G06F2212/1016 ,  G06F2212/20 ,  G06F2212/60 ,  G06F2212/601

Abstract: Providing flexible management of heterogeneous memory systems using spatial Quality of Service (QoS) tagging in processor-based systems is disclosed. In one aspect, a heterogeneous memory system of a processor-based system includes a first memory and a second memory. The heterogeneous memory system is divided into a plurality of memory regions, each associated with a QoS identifier (QoSID), which may be set and updated by software. A memory controller of the heterogeneous memory system provides a QoS policy table, which operates to associate each QoSID with a QoS policy state, and which also may be software-configurable. Upon receiving a memory access request including a memory address of a memory region, the memory controller identifies a software-configurable QoSID associated with the memory address, and associates the QoSID with a QoS policy state using the QoS policy table. The memory controller then applies the QoS policy state to perform the memory access operation.