公开(公告)号：US10382190B1

公开(公告)日：2019-08-13

申请号：US16035575

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Rajeev Sharma ,  Santhosh Kumar Gude ,  Parth Patel ,  Hadi Goudarzi ,  Eskinder Hailu

IPC: H04L7/00 ,  H04L7/033 ,  G06F1/26 ,  G06F13/362

Abstract: A desirable feature of a SERDES design is power savings. One way to achieve power savings is by keeping the CDR circuit OFF during most of the time when a link is active between a transmitter and a receiver. However, due to voltage supply noise, temperature fluctuations and uncorrelated crosstalk, the receiver data may shift and/or the eye may collapse if the CDR is not turned ON to take care of these modulations. To address such disadvantages, it is proposed to generate a CDR profile that can specify optimum CDR ON and OFF time so that link stability may be maintained while saving power.