公开(公告)号：US12106793B2

公开(公告)日：2024-10-01

申请号：US18081442

申请日：2022-12-14

Applicant: QUALCOMM Incorporated

Inventor： Saurabh Sethi ,  Madhukar Reddy N ,  Vasantha Kumar Bandur Puttappa ,  Amulya Srinivasan Margasahayam

IPC: G11C11/40 ,  G11C11/406 ,  G11C11/4093

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4093

Abstract: Aspects of the present disclosure are directed to techniques and procedures for reducing memory (e.g., DRAM) access latency (e.g., read latency, write latency) due to memory refreshes. In some aspects, a memory refresh scheduling algorithm can take into account of memory access batching (e.g., read batch, write batch). In some aspects, a refresh scheduling algorithm can schedule more or prioritize refreshes to occur during a write batch to reduce memory read access latency because fewer refreshes are scheduled during memory read access. The techniques can be adapted to reduce write latency.