公开(公告)号：US11290109B1

公开(公告)日：2022-03-29

申请号：US17030087

申请日：2020-09-23

Applicant: QUALCOMM Incorporated

Inventor： Foua Vang ,  Hyeokjin Lim ,  Seung Hyuk Kang ,  Venugopal Boynapalli ,  Shitiz Arora

IPC: H01L21/00 ,  H03K19/094 ,  H01L23/528

Abstract: A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mx layer interconnects on an Mx layer extending in a first direction over the first and second subcells. A first subset of the first set of Mx layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mx layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.