Successive approximation register (SAR) analog-to-digital converter (ADC) with passive gain scaling

    公开(公告)号:US10277244B1

    公开(公告)日:2019-04-30

    申请号:US16046053

    申请日:2018-07-26

    Abstract: Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a passive gain scaling architecture. Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a plurality of capacitive elements, a plurality of switches coupled to the plurality of capacitive elements, and SAR logic having an output coupled to control inputs of the plurality of switches. The circuit also includes a comparator having an output coupled to an input of the SAR logic, a sampling circuit coupled to an input node of the circuit, and a first capacitive element coupled in series between the sampling circuit and the plurality of capacitive elements.

    APPARATUS AND METHOD FOR REDUCING AMPLIFIER FEEDBACK CAPACITOR WITH BYPASS AMPLIFICATION STAGE

    公开(公告)号:US20190294295A1

    公开(公告)日:2019-09-26

    申请号:US15926728

    申请日:2018-03-20

    Abstract: A touchscreen controller includes a set of transmitters for generating transmit signals applied to electrically-conductive transmit lines of a touchscreen panel, and a set of receivers configured to receive the signals via electrically-conductive receive lines that are capacitively coupled to the transmit lines. Each receiver includes an integrator to integrate the received current signal to generate an output voltage used for determining a location, if any, of a finger or object touching the panel. The integrator includes input and output amplification stages, and a feedback capacitor coupled between an input and output of the cascaded amplification stages. The capacitance of the feedback capacitor is configured so that the integrator achieves a desired rejection of a received jammer current signal. To reduce the size of the feedback capacitor, a bypass amplification stage is provided to steer away some of the input jammer current from the input of the integrator.

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