公开(公告)号：US09697320B2

公开(公告)日：2017-07-04

申请号：US14864156

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Sreedhar Gudala ,  Kumar Gopal Rao ,  Francis Page ,  Pak Kin Wong ,  Sunil Kumar

IPC: G06F17/50 ,  G06F15/78 ,  G06F11/14 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F17/5072 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1423 ,  G06F12/0646 ,  G06F15/7807 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2212/2542 ,  G06F2213/0038 ,  G06F2217/66

Abstract: Circuits and methods for a system on a chip having non-uniform channel spacings is provided. In an example, a chip is provided that includes a first functional block having a rectilinear shape, the first processing unit having on a side a plurality of channel spacings. A first channel spacing of the plurality of channel spacings is positioned in contact with the side and a second functional block. A second channel spacing of the plurality of channel spacings is positioned in contact with the side and the second functional block. The width of the second channel spacing is non-uniform with the width of the first channel spacing.

公开(公告)号：US20180342460A1

公开(公告)日：2018-11-29

申请号：US15605843

申请日：2017-05-25

Applicant: QUALCOMM Incorporated

Inventor： Sreedhar Gudala ,  Paras Gupta ,  Ranganayakulu Konduri

IPC: H01L23/528 ,  H01L23/48 ,  G06F17/50

Abstract: In certain aspects of the disclosure, a chip includes a power distribution network for distributing power to device on the chip. The power distribution network includes a first portion formed from a first metal layer on the chip, a second portion formed from a second metal layer on the chip, and vias interconnecting the first and second portions of the power distribution network, wherein the vias include a first plurality of vias and a second plurality of vias, each one of the first plurality of vias has a first via size, and each one of the second plurality of vias has a second via size. The devices on the chip are electrically coupled to the first portion of the power distribution network.

公开(公告)号：US20170091365A1

公开(公告)日：2017-03-30

申请号：US14864156

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Sreedhar Gudala ,  Kumar Gopal Rao ,  Francis Page ,  Pak Kin Wong ,  Sunil Kumar

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1423 ,  G06F12/0646 ,  G06F15/7807 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2212/2542 ,  G06F2213/0038 ,  G06F2217/66

Abstract: Circuits and methods for a system on a chip having non-uniform channel spacings is provided. In an example, a chip is provided that includes a first functional block having a rectilinear shape, the first processing unit having on a side a plurality of channel spacings. A first channel spacing of the plurality of channel spacings is positioned in contact with the side and a second functional block. A second channel spacing of the plurality of channel spacings is positioned in contact with the side and the second functional block. The width of the second channel spacing is non-uniform with the width of the first channel spacing.