公开(公告)号：US20240202087A1

公开(公告)日：2024-06-20

申请号：US18498583

申请日：2023-10-31

Applicant: QUALCOMM Incorporated

Inventor： Sreeram Jayadev ,  Vinod Chamarty

IPC: G06F11/22

CPC classification number: G06F11/2221

Abstract: Routing raw debug data using trace infrastructure in processor-based devices is disclosed. In some aspects, a processor-based device comprises a trace interconnect bus, a subsystem circuit comprising a debug transmit circuit, and an input/output (I/O) endpoint circuit. The debug transmit circuit is configured to receive raw debug data from the subsystem circuit, and generate a debug trace packet comprising the raw debug data in lieu of formatted trace data. The debug transmit circuit is also configured to transmit the debug trace packet comprising the raw debug data to the I/O endpoint circuit via the trace interconnect bus during a period of trace interconnect bus inactivity. In this manner, an existing trace infrastructure can be employed to transmit raw debug data without incurring expense in terms of overhead and monetary cost due to the need for industry-standard, infrastructure-compliant tools to decode conventionally packetized trace data for analysis.

公开(公告)号：US20240427393A1

公开(公告)日：2024-12-26

申请号：US18626683

申请日：2024-04-04

Applicant: QUALCOMM Incorporated

Inventor： Vinod Chamarty ,  Sagar Koorapati ,  Sreeram Jayadev ,  Alon Naveh

IPC: G06F1/26

Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.

公开(公告)号：US20240427392A1

公开(公告)日：2024-12-26

申请号：US18339430

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Vinod Chamarty ,  Sagar Koorapati ,  Sreeram Jayadev ,  Alon Naveh

IPC: G06F1/26

Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.