公开(公告)号：US20240427411A1

公开(公告)日：2024-12-26

申请号：US18626645

申请日：2024-04-04

Applicant: QUALCOMM Incorporated

Inventor： Vinod Chamarty ,  Sagar Koorapati ,  Alon Naveh

IPC: G06F1/3293

Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. To mitigate the delay in the reporting of activity power event of a monitored processing device that may affect throttling of power consumption for the IC chip, the power consumption of a monitored processing device can also be throttled locally throttle its power consumption. This gives reaction time for the power management system to receive and process activity power events to throttle power consumption in the IC chip.

公开(公告)号：US20240427400A1

公开(公告)日：2024-12-26

申请号：US18623217

申请日：2024-04-01

Applicant: QUALCOMM Incorporated

Inventor： Sagar Koorapati ,  Vinod Chamarty ,  Gaurav Sanjeev Kirtane ,  Pushkin Raj Pari ,  Nitin Makhija ,  Alon Naveh

IPC: G06F1/28

Abstract: The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.

公开(公告)号：US20240427396A1

公开(公告)日：2024-12-26

申请号：US18339436

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sagar Koorapati ,  Alon Naveh

IPC: G06F1/28

Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The hierarchical power management system includes a centralized power estimation and limiting (PEL) circuit that is configured to track and merge received power throttle recommendations associated with related activity power events for monitored processing devices to generate one or more power limiting management responses to throttle power consumption of related devices that may be contributing to excess power consumption.

公开(公告)号：US20240427397A1

公开(公告)日：2024-12-26

申请号：US18339447

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sagar Koorapati ,  Vinod Chamarty ,  Gaurav Sanjeev Kirtane ,  Pushkin Raj Pari ,  Nitin Makhija ,  Alon Naveh

IPC: G06F1/28

Abstract: The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.

公开(公告)号：US20240427368A1

公开(公告)日：2024-12-26

申请号：US18339478

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sagar Koorapati ,  Alon Naveh

IPC: G06F1/08 ,  G06F1/3228 ,  G06F1/324

Abstract: A throttle control circuit receives a throttle control signal for controlling power consumption in a plurality of processing segment circuits. The throttle control signal has a throttle control value based on throttle requests from monitoring circuits that have detected power-related events or conditions and correspond to a requested change in activity in the plurality of processing segment circuits. The throttle control circuit receives the throttle control signal in a plurality of throttle administration circuits that each generates a throttle select signal to select an activity control signal for a corresponding processing segment circuit. In each of a first number (N) of consecutive cycles of a clock signal, the activity control signal disables state changes in the corresponding processing segment circuit for a second number (M) of cycles among the first number (N) of consecutive cycles to reduce power consumption in the processing segment circuits.

公开(公告)号：US20240428024A1

公开(公告)日：2024-12-26

申请号：US18339504

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sagar Koorapati ,  Vinod Chamarty ,  Alon Naveh

IPC: G06K7/10

Abstract: Broadcasting power limiting management responses in a processor-based system in an integrated circuit (IC) chip is disclosed herein. In one aspect, an IC chip comprises a processor-based system that includes a power estimation and limiting (PEL) circuit, a Limit Management Throughput Throttle (LMTT) source circuit, a plurality of activity management (AM) circuits, and an LMTT bus communicatively coupling the LMTT source circuit with each AM circuit of the plurality of AM circuits. The LMTT source circuit receives a power limiting management response from a PEL circuit via a communications network of the processor-based system, and generates an LMTT command based on the power limiting management response. The LMTT source circuit broadcasts the LMTT command to each AM circuit of the plurality of AM circuits via the LMTT bus.

公开(公告)号：US20240427682A1

公开(公告)日：2024-12-26

申请号：US18339520

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sagar Koorapati ,  Pradeep Kanapathipillai ,  Alon Naveh

IPC: G06F11/30 ,  G06F1/3206

Abstract: Converting telemetry values into common data formats in a processor-based system in an integrated circuit (IC) chip is disclosed herein. In one aspect, an IC chip comprises a processor-based system that that is configured to receive an input telemetry value from an input source circuit. The processor-based system converts the input telemetry value into a common format telemetry value, wherein a first unit value represented by a least significant bit of the common format telemetry value is greater than one (1) and is based on a quotient of a power of two (2) and a corresponding power of 10. The processor-based system then processes common format telemetry value.

公开(公告)号：US20240427393A1

公开(公告)日：2024-12-26

申请号：US18626683

申请日：2024-04-04

Applicant: QUALCOMM Incorporated

Inventor： Vinod Chamarty ,  Sagar Koorapati ,  Sreeram Jayadev ,  Alon Naveh

IPC: G06F1/26

Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.

公开(公告)号：US20240427392A1

公开(公告)日：2024-12-26

申请号：US18339430

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Vinod Chamarty ,  Sagar Koorapati ,  Sreeram Jayadev ,  Alon Naveh

IPC: G06F1/26

Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.

公开(公告)号：US12228988B2

公开(公告)日：2025-02-18

申请号：US18339436

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sagar Koorapati ,  Alon Naveh

IPC: G06F1/32 ,  G06F1/28 ,  G06F1/3203

Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The hierarchical power management system includes a centralized power estimation and limiting (PEL) circuit that is configured to track and merge received power throttle recommendations associated with related activity power events for monitored processing devices to generate one or more power limiting management responses to throttle power consumption of related devices that may be contributing to excess power consumption.