公开(公告)号：US11169940B2

公开(公告)日：2021-11-09

申请号：US16736542

申请日：2020-01-07

Applicant: QUALCOMM Incorporated

Inventor： Sunil Gupta ,  Scott Powers

IPC: G06F13/16 ,  H05K1/18 ,  H05K1/02 ,  G06F3/06

Abstract: A wireline communications system is described. The wireline communications system includes a printed circuit board (PCB). The wireline communications system also includes a system on chip (SoC) die on the PCB. The wireline communications system further includes an external memory device coupled to a memory interface of the SoC die. The external memory device is coupled to the memory interface of the SoC die through a PCB trace. A length of the PCB trace is configured according to an operating speed of the memory interface.

公开(公告)号：US11443776B2

公开(公告)日：2022-09-13

申请号：US16442208

申请日：2019-06-14

Applicant: QUALCOMM Incorporated

Inventor： Sunil Gupta

IPC: G11C5/06 ,  H01L25/18

Abstract: An integrated circuit is described. The integrated circuit (IC) may include a printed circuit board (PCB). The IC may also include a system on chip (SoC) die on the PCB. The IC may further include a memory device coupled to a parallel memory interface of the SoC die. The memory device may be coupled to a parallel memory interface through parallel signal traces arranged in an asymmetric routing. In the asymmetric routing of the parallel signal traces, the signal traces are arranged according to a variable spacing is between the parallel signal traces for a majority portion of the parallel signal traces.