公开(公告)号：US20240320408A1

公开(公告)日：2024-09-26

申请号：US18187198

申请日：2023-03-21

Applicant: QUALCOMM Incorporated

Inventor： Gokce SARAR ,  Guillaume SHIPPEE ,  Rhys BUGGY ,  Santanu PATTANAYAK ,  Tushit JAIN ,  Suman Kumar GUNNALA ,  Kumar RAJ ,  Vatsal Nimeshkumar THAKKAR

IPC: G06F30/333 ,  G06N3/084

CPC classification number: G06F30/333 ,  G06N3/084

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for testing integrated circuit designs. An example method generally includes generating a coverage matrix associated with a plurality of test cases for an integrated circuit and coverage points associated with each test case of the plurality of test cases. A subset of the plurality of test cases is selected for execution based on weights associated with each test case of the plurality of test cases and a threshold weight value. Generally, the weights associated with each test case comprise weights in a machine learning model trained based on the coverage matrix. The integrated circuit may be tested based on the selected subset of test cases.

公开(公告)号：US20230102185A1

公开(公告)日：2023-03-30

申请号：US17484536

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Lindsey Makana KOSTAS ,  Santanu PATTANAYAK ,  Tushit JAIN

IPC: G06F30/3315 ,  G06N3/04

Abstract: Certain aspects of the present disclosure provide techniques for testing integrated circuit designs based on test cases selected using machine learning models. An example method generally includes receiving a plurality of test cases for an integrated circuit. An embedding data set is generated from the plurality of test cases. A respective embedding for a respective test case of the plurality of test cases generally includes a mapping of the respective test case into a multidimensional space. A plurality of test case clusters is generated based on a clustering model and the embedding data set. A plurality of critical test cases for testing the integrated circuit is selected based on the plurality of test case clusters. The integrated circuit is timed based on the plurality of critical test cases and a hard macro defining the integrated circuit.