公开(公告)号：US20230058318A1

公开(公告)日：2023-02-23

申请号：US17404919

申请日：2021-08-17

Applicant: QUALCOMM Incorporated

Inventor： Udayakiran Kumar YALLAMARAJU ,  Xia LI ,  Pankaj DESHMUKH ,  Vajram GHANTASALA ,  Bin YANG ,  Vishal MISHRA ,  Bharatheesha Sudarshan JAGIRDAR ,  Arun Sundaresan IYER ,  Amod PHADKE ,  Vanamali BHAT

IPC: H03K5/156 ,  H03K5/134

Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.

公开(公告)号：US20250155916A1

公开(公告)日：2025-05-15

申请号：US18509245

申请日：2023-11-14

Applicant: QUALCOMM Incorporated

Inventor： Vanamali BHAT ,  Amod PHADKE ,  Sina DENA ,  Michael TIPTON ,  Amit ANEJA ,  Prachin Sheshrao BHOYAR

IPC: G06F1/08 ,  B60W50/06

Abstract: A method for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating is described. The method includes generating a set of clocks. The method also includes routing a selected one of the set of clocks for frequency measurement through one or more clock routing subsystems. The method further includes adjusting a frequency of the selected clock after the selected clock is routed through the clock routing subsystems. The method also includes communicating a sideband signal to indicate the adjusted frequency of the selected clock.