公开(公告)号：US20240231982A9

公开(公告)日：2024-07-11

申请号：US18489809

申请日：2023-10-18

Applicant: QUALCOMM Incorporated

Inventor： Amit ANEJA ,  Vasant Kumar EASWARAN ,  Rahul GULATI

IPC: G06F11/07

CPC classification number: G06F11/0745 ,  G06F11/079 ,  G06F11/0793

Abstract: Aspects of the present disclosure provide techniques and apparatus for safety monitoring of a vehicle control system. An example method of operating a vehicle includes detecting an error associated with a system-on-a-chip (SoC) having a main domain and a safety domain, wherein the main domain is coupled to a first bus for communicating with one or more electronic control units (ECUs) and wherein the safety domain is coupled to a second bus for communicating with the one or more ECUs; indicating the error to the one or more ECUs via at least one of the first bus, the second bus, or a power management integrated circuit (PMIC) in response to detecting the error, wherein the PMIC is configured to supply power to the main domain or the safety domain; and performing one or more actions in response to detecting the error.

公开(公告)号：US20250028890A1

公开(公告)日：2025-01-23

申请号：US18482681

申请日：2023-10-06

Applicant: QUALCOMM Incorporated

Inventor： Anatoly GELMAN ,  Michael James SMITH ,  James Cheng-Huan WU ,  Olivier ALAVOINE ,  Amit ANEJA

IPC: G06F30/343 ,  G06F30/327

Abstract: Aspects relate to monitoring timing. In one example an apparatus includes a first sensor array formed in an integrated circuit, sensors of the first sensor array having paths through the integrated circuit and sensors of the first sensor array configured to generate one or more first level indications of a condition of the integrated circuit. A second sensor array is formed in the integrated circuit. Sensors of the second sensor array have paths through the integrated circuit and sensors of the second sensor array are configured to generate one or more second level indications of the condition of the integrated circuit. A monitor controller is coupled to the first sensor array and to the second sensor array and configured to receive the one or more first level indications and to actuate the second sensor array in response to the one or more first level indications.

公开(公告)号：US20250155916A1

公开(公告)日：2025-05-15

申请号：US18509245

申请日：2023-11-14

Applicant: QUALCOMM Incorporated

Inventor： Vanamali BHAT ,  Amod PHADKE ,  Sina DENA ,  Michael TIPTON ,  Amit ANEJA ,  Prachin Sheshrao BHOYAR

IPC: G06F1/08 ,  B60W50/06

Abstract: A method for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating is described. The method includes generating a set of clocks. The method also includes routing a selected one of the set of clocks for frequency measurement through one or more clock routing subsystems. The method further includes adjusting a frequency of the selected clock after the selected clock is routed through the clock routing subsystems. The method also includes communicating a sideband signal to indicate the adjusted frequency of the selected clock.

公开(公告)号：US20240296702A1

公开(公告)日：2024-09-05

申请号：US18176902

申请日：2023-03-01

Applicant: QUALCOMM INCORPORATED

Inventor： Amit ANEJA ,  Rahul GULATI ,  Sriram HARIHARAN

IPC: G07C5/08 ,  G01R31/00

CPC classification number: G07C5/0808 ,  G01R31/007 ,  B60R16/023 ,  B60W50/0225

Abstract: Fail-safe and Fail-operational behavior can be achieved by providing two fully-redundant execution channels comprising at least first and second chiplet dies on a single SoC that are in communication with one another via a D2D interface. At least first and second instances of a first automotive safety integrity level (ASIL) domain circuit disposed on the at least first and second chiplet dies, respectively, perform at least a first ASIL domain process on one or more automotive sensor output signals to produce first and second output signals, respectively. A fault monitoring system monitors at least the first chiplet die for faults and assigns a first value to a selector signal if it detects a fault in the first chiplet die. A selector circuit outputs the second output signal from the system if the selector signal has the first value.

公开(公告)号：US20250027996A1

公开(公告)日：2025-01-23

申请号：US18482703

申请日：2023-10-06

Applicant: QUALCOMM Incorporated

Inventor： Anatoly GELMAN ,  Michael James SMITH ,  James Cheng-Huan WU ,  Olivier ALAVOINE ,  Amit ANEJA

IPC: G01R31/3185

Abstract: Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an apparatus includes an integrated circuit having a logic path formed in the integrated circuit and a monitor circuit formed in the integrated circuit. The monitor circuit is configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to store the diagnostic codes in a log with a corresponding time stamp and to determine a condition of the integrated circuit based on the diagnostic code sequence.

公开(公告)号：US20240134730A1

公开(公告)日：2024-04-25

申请号：US18489809

申请日：2023-10-17

Applicant: QUALCOMM Incorporated

Inventor： Amit ANEJA ,  Vasant Kumar EASWARAN ,  Rahul GULATI

IPC: G06F11/07

CPC classification number: G06F11/0745 ,  G06F11/079 ,  G06F11/0793

Abstract: Aspects of the present disclosure provide techniques and apparatus for safety monitoring of a vehicle control system. An example method of operating a vehicle includes detecting an error associated with a system-on-a-chip (SoC) having a main domain and a safety domain, wherein the main domain is coupled to a first bus for communicating with one or more electronic control units (ECUs) and wherein the safety domain is coupled to a second bus for communicating with the one or more ECUs; indicating the error to the one or more ECUs via at least one of the first bus, the second bus, or a power management integrated circuit (PMIC) in response to detecting the error, wherein the PMIC is configured to supply power to the main domain or the safety domain; and performing one or more actions in response to detecting the error.

公开(公告)号：US20250052812A1

公开(公告)日：2025-02-13

申请号：US18447446

申请日：2023-08-10

Applicant: QUALCOMM Incorporated

Inventor： Amit ANEJA ,  Dipti Ranjan PAL ,  Kiran Kumar MALIPEDDI

IPC: G01R31/317

Abstract: Methods and apparatuses directed to. In some examples, a die package includes voltage logic that provides a voltage to a voltage rail, clock logic that generates a clock signal, and adaptive clock distribution logic that receives the clock signal and the voltage. The adaptive clock distribution logic can increment an event count when the clock signal is above a threshold frequency, or when the voltage is below a threshold voltage level. The die package also includes a processor that can monitor the event counts during operation and determine a status of the adaptive clock distribution logic based on the event counts. In some examples, the processor can test the adaptive clock distribution logic by causing the clock signal to operate above the threshold frequency, or causing the voltage logic to provide the voltage below the threshold voltage level. The processor can then read the event counts to determine the status.

公开(公告)号：US20250028377A1

公开(公告)日：2025-01-23

申请号：US18482749

申请日：2023-10-06

Applicant: QUALCOMM Incorporated

Inventor： Anatoly GELMAN ,  Michael James SMITH ,  James Cheng-Huan WU ,  Olivier ALAVOINE ,  Amit ANEJA

IPC: G06F1/3228 ,  G06F1/3296 ,  G06F11/27

Abstract: Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an integrated circuit has a logic path formed in the integrated circuit. A monitor circuit is formed in the integrated circuit near the logic path and configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to determine a condition of the integrated circuit based on the diagnostic code sequence, and to initiate a remedial action in response to the condition of the integrated circuit.

公开(公告)号：US20240227825A1

公开(公告)日：2024-07-11

申请号：US18152222

申请日：2023-01-10

Applicant: QUALCOMM Incorporated

Inventor： Amit ANEJA ,  Rahul GULATI

IPC: B60W50/02 ,  B60W50/00 ,  B60W50/035 ,  G07C5/08

CPC classification number: B60W50/0205 ,  B60W50/0098 ,  B60W50/035 ,  G07C5/085

Abstract: Aspects of the present disclosure provide techniques and apparatus for testing a mixed safety system, such as system included in a vehicle. An example method of operating a vehicle includes operating an electronic control unit (ECU) in a first state; detecting one or more criteria being satisfied to perform a test associated with the ECU; and performing the test associated with the ECU in response to detecting the one or more criteria being satisfied, while the ECU is in a second state different from the first state.

公开(公告)号：US20240067110A1

公开(公告)日：2024-02-29

申请号：US18457066

申请日：2023-08-28

Applicant: QUALCOMM Incorporated

Inventor： Amit ANEJA ,  Vasant Kumar EASWARAN ,  Rahul GULATI

IPC: B60R16/03 ,  B60R16/023

CPC classification number: B60R16/03 ,  B60R16/0232

Abstract: Techniques and apparatus for power supply monitoring in in-vehicle systems, such as advanced driver assistance systems (ADASs), in-vehicle infotainment (IVI) systems, and/or automated driving (AD) systems. One example method of power supply monitoring generally includes regulating power to a main domain of a system on a chip (SoC) using at least one main domain (MD) power management integrated circuit (PMIC); regulating power to a safety domain of the SoC using at least one safety domain (SD) PMIC; powering the at least one SD PMIC using a SD PMIC power supply rail; and monitoring the SD PMIC power supply rail using the at least one MD PMIC. For certain aspects, the method further includes powering the at least one MD PMIC using a MD PMIC power supply rail and monitoring the MD PMIC power supply rail using the at least one SD PMIC.