公开(公告)号：US20150249546A1

公开(公告)日：2015-09-03

申请号：US14430195

申请日：2012-10-29

Applicant: Xiangyang ZHENG ,  Patrick K.M. TSE ,  Yue CAO ,  Yuan LI ,  QUALCOMM INCORPORATED

Inventor： Xiangyang Zheng ,  Patrick Tse ,  Yue Cao ,  Yuan Li

IPC: H04L12/403 ,  H04J3/16

CPC classification number: H04L12/4035 ,  H04J3/1694 ,  H04L47/621

Abstract: A method of transmitting data includes storing high-priority data blocks in a high-priority queue, storing low-priority data blocks in a low-priority queue, and generating a first data unit that includes one or more of the high-priority data blocks and one or more of the low-priority data blocks. Generating the first data unit includes arranging the one or more high-priority data blocks and the one or more low-priority data blocks in a sequence in which the one or more high-priority data blocks precede the one or more low-priority data blocks. Generating the first data unit further includes indexing the one or more high-priority data blocks and the one or more low-priority data blocks in accordance with the sequence. The first data unit is transmitted.

Abstract translation: 一种发送数据的方法包括将高优先级数据块存储在高优先级队列中，将低优先级数据块存储在低优先级队列中，以及生成包括一个或多个高优先级数据块的第一数据单元 以及一个或多个低优先级数据块。 生成第一数据单元包括在一个或多个高优先级数据块在一个或多个低优先级数据块之前的序列中排列一个或多个高优先级数据块和一个或多个低优先级数据块 。 生成第一数据单元还包括根据序列索引一个或多个高优先级数据块和一个或多个低优先级数据块。 发送第一个数据单元。

公开(公告)号：US11437307B2

公开(公告)日：2022-09-06

申请号：US16949695

申请日：2020-11-11

Applicant: QUALCOMM Incorporated

Inventor： Abdolreza Langari ,  Yuan Li ,  Shrestha Ganguly ,  Terence Cheung ,  Ching-Liou Huang ,  Hui Wang

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.

公开(公告)号：US10916494B2

公开(公告)日：2021-02-09

申请号：US16453803

申请日：2019-06-26

Applicant: QUALCOMM Incorporated

Inventor： Abdolreza Langari ,  Yuan Li ,  Shrestha Ganguly ,  Terence Cheung ,  Ching-Liou Huang ,  Hui Wang

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.