公开(公告)号：US20230118028A1

公开(公告)日：2023-04-20

申请号：US17451302

申请日：2021-10-18

Applicant: QUALCOMM Incorporated

Inventor： Michelle Yejin Kim ,  Kuiwon Kang ,  Joan Rey Villarba Buot ,  Ching-Liou Huang

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Integrated circuit (IC) packages employing a supplemental metal layer with coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer to reduce metal density mismatch, and related fabrication methods. An IC package includes a semiconductor die (“die”) electrically coupled to a package substrate. The package substrate includes a die-side ETS metallization layer adjacent to and coupled to the die. To reduce or avoid metal density mismatch between the die-side ETS metallization layer and another metallization layer(s) in the package substrate, a supplemental metal layer with additional metal interconnects is disposed adjacent to the die-size ETS metallization layer. The additional metal interconnects are coupled in a vertical direction to the embedded metal traces in the die-side ETS metallization layer to increase metal density of die-side metal interconnects formed by the additional metal interconnects coupled to the embedded metal traces in the die-side ETS metallization layer.

公开(公告)号：US11437307B2

公开(公告)日：2022-09-06

申请号：US16949695

申请日：2020-11-11

Applicant: QUALCOMM Incorporated

Inventor： Abdolreza Langari ,  Yuan Li ,  Shrestha Ganguly ,  Terence Cheung ,  Ching-Liou Huang ,  Hui Wang

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.

公开(公告)号：US10916494B2

公开(公告)日：2021-02-09

申请号：US16453803

申请日：2019-06-26

Applicant: QUALCOMM Incorporated

Inventor： Abdolreza Langari ,  Yuan Li ,  Shrestha Ganguly ,  Terence Cheung ,  Ching-Liou Huang ,  Hui Wang

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.