METHOD OF GENERATING PRECISE AND PVT-STABLE TIME DELAY OR FREQUENCY USING CMOS CIRCUITS

    公开(公告)号:US20210194474A1

    公开(公告)日:2021-06-24

    申请号:US17022608

    申请日:2020-09-16

    Abstract: A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

    POWER AND AREA EFFICIENT DIGITAL-TO-TIME CONVERTER WITH IMPROVED STABILITY

    公开(公告)号:US20220182065A1

    公开(公告)日:2022-06-09

    申请号:US17449250

    申请日:2021-09-28

    Abstract: A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

Patent Agency Ranking